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参数资料
| 型号： | HYS72T64000EP-3.7-B2 |
| 厂商： | QIMONDA AG |
| 元件分类： | DRAM |
| 英文描述： | 64M X 72 DDR DRAM MODULE, DMA240 |
| 封装： | GREEN, RDIMM-240 |
| 文件页数： | 13/64页 |
| 文件大小： | 3411K |
| 代理商： | HYS72T64000EP-3.7-B2 |
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HYS72T[64/128/256]xx0EP–[2.5/25F/3/3S/3.7]–B2
Registered DDR2 SDRAM Modules
Internet Data Sheet
Rev. 1.02, 2008-06
20
07312007-HYD2-P177
6) The output timing reference voltage level is
V
TT.
7) New units, ‘
t
CK.AVG‘ and ‘nCK‘, are introduced in DDR2–667 and DDR2–800. Unit ‘tCK.AVG‘ represents the actual tCK.AVG of the input clock
under operation. Unit ‘nCK‘ represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2–400 and
DDR2–533, ‘
t
CK‘ is used for both concepts. Example: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command
may be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x
t
CK.AVG + tERR.2PER(Min).
8) When the device is operated with input clock jitter, this parameter needs to be derated by the actual
t
ERR(6-10per) of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has
t
ERR(6-10PER).MIN = – 272
ps and
t
ERR(6- 10PER).MAX = + 293 ps, then tDQSCK.MIN(DERATED) = tDQSCK.MIN – tERR(6-10PER).MAX = – 400 ps – 293 ps = – 693 ps and
t
DQSCK.MAX(DERATED) = tDQSCK.MAX – tERR(6-10PER).MIN = 400 ps + 272 ps = + 672 ps. Similarly, tLZ.DQ for DDR2–667 derates to tLZ.DQ.MIN(DERATED)
= - 900 ps – 293 ps = – 1193 ps and
t
LZ.DQ.MAX(DERATED) = 450 ps + 272 ps = + 722 ps. (Caution on the MIN/MAX usage!)
9) Input clock jitter spec parameter. The jitter specified is a random jitter meeting a Gaussian distribution.
10) These parameters are specified per their average values.
11)
t
CKE.MIN of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the
entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during
the time period of
t
IS + 2 x tCK + tIH.
12) DAL = WR + RU{
t
RP(ns) / tCK(ns)}, where RU stands for round up. WR refers to the tWR parameter stored in the MRS. For tRP, if the result
of the division is not already an integer, round up to the next highest integer.
t
CK refers to the application clock period. Example: For
DDR2–533 at
t
CK = 3.75 ns with tWR programmed to 4 clocks. tDAL = 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks.
13)
t
DAL.nCK = WR [nCK] + tnRP.nCK = WR + RU{tRP [ps] / tCK.AVG[ps] }, where WR is the value programmed in the EMR.
14) Input waveform timing
t
DH with differential data strobe enabled MR[bit10] = 0, is referenced from the differential data strobe crosspoint to
the input signal crossing at the
V
IH.DC level for a falling signal and from the differential data strobe crosspoint to the input signal crossing
at the
V
IL.DC level for a rising signal applied to the device under test. DQS, DQS signals must be monotonic between VIL.DC.MAX and
V
IH.DC.MIN. See Figure 3.
15)
t
DQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output
slew rate mismatch between DQS / DQS and associated DQ in any given cycle.
16) These parameters are measured from a data strobe signal ((L/U/R)DQS / DQS) crossing to its respective clock signal (CK / CK) crossing.
The spec values are not affected by the amount of clock jitter applied (i.e.
t
JIT.PER, tJIT.CC, etc.), as these are relative to the clock signal
crossing. That is, these parameters should be met whether clock jitter is present or not.
17) Input waveform timing
t
DS with differential data strobe enabled MR[bit10] = 0, is referenced from the input signal crossing at the VIH.AC level
to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the
V
IL.AC level to the differential data strobe
crosspoint for a falling signal applied to the device under test. DQS, DQS signals must be monotonic between
V
il(DC)MAX and Vih(DC)MIN. See
18) If
t
DS or tDH is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed.
19) These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge to its respective data strobe signal
((L/U/R)DQS / DQS) crossing.
20)
t
HP is the minimum of the absolute half period of the actual input clock. tHP is an input parameter but not an input specification parameter.
It is used in conjunction with t
QHS to derive the DRAM output timing tQH. The value to be used for tQH calculation is determined by the
following equation;
t
HP = MIN (tCH.ABS, tCL.ABS), where, tCH.ABS is the minimum of the actual instantaneous clock high time; tCL.ABS is the
minimum of the actual instantaneous clock low time.
21)
t
HZ and tLZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level
which specifies when the device output is no longer driving (
t
HZ), or begins driving (tLZ) .
22) input waveform timing is referenced from the input signal crossing at the
V
IL.DC level for a rising signal and VIH.DC for a falling signal applied
to the device under test. See Figure 4.
23) Input waveform timing is referenced from the input signal crossing at the
V
IH.AC level for a rising signal and VIL.AC for a falling signal applied
to the device under test. See Figure 4.
24) These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition edge to
its respective clock signal (CK / CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e.
t
JIT.PER, tJIT.CC,
etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should
be met whether clock jitter is present or not.
25)
t
QH = tHP – tQHS, where: tHP is the minimum of the absolute half period of the actual input clock; and tQHS is the specification value under
the max column. {The less half-pulse width distortion present, the larger the
t
QH value is; and the larger the valid data eye will be.}
Examples: 1) If the system provides
t
HP of 1315 ps into a DDR2–667 SDRAM, the DRAM provides tQH of 975 ps minimum. 2) If the system
provides
t
HP of 1420 ps into a DDR2–667 SDRAM, the DRAM provides tQH of 1080 ps minimum.
26)
t
QHS accounts for: 1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual tHP at the input is
transferred to the output; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next
transition, both of which are independent of each other, due to data pin skew, output pattern effects, and pchannel to n-channel variation
of the output drivers.
27) The Auto-Refresh command interval has be reduced to 3.9 s when operating the DDR2 DRAM in a temperature range between 85
°C
and 95
°C.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| HYS72T64000EU-2.5-B2 | 制造商:QIMONDA 制造商全称:QIMONDA 功能描述:240-Pin unbuffered DDR2 SDRAM Modules |
| HYS72T64000EU-25F-B2 | 制造商:QIMONDA 制造商全称:QIMONDA 功能描述:240-Pin unbuffered DDR2 SDRAM Modules |
| HYS72T64000EU-3.7-B2 | 制造商:QIMONDA 制造商全称:QIMONDA 功能描述:240-Pin unbuffered DDR2 SDRAM Modules |
| HYS72T64000EU-3-B2 | 制造商:QIMONDA 制造商全称:QIMONDA 功能描述:240-Pin unbuffered DDR2 SDRAM Modules |
| HYS72T64000EU-3S-B2 | 制造商:QIMONDA 制造商全称:QIMONDA 功能描述:240-Pin unbuffered DDR2 SDRAM Modules |
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