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参数资料
| 型号： | IBM25403GCX-3JC76C2 |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | RISC PROCESSOR, PQFP16 |
| 封装： | PLASTIC, QFP-160 |
| 文件页数： | 5/54页 |
| 文件大小： | 541K |
| 代理商： | IBM25403GCX-3JC76C2 |
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IBM PowerPC 403GCX
13
GND
90
K13
Ground. All ground pins must be used.
101
G12
Ground. All ground pins must be used.
102
H12
Ground. All ground pins must be used.
111
E12
Ground. All ground pins must be used.
121
G8
Ground. All ground pins must be used.
130
B10
Ground. All ground pins must be used.
141
C7
Ground. All ground pins must be used.
150
A5
Ground. All ground pins must be used.
Halt
9
D4
I
Halt from external debugger, active low.
HoldAck
134
B9
O
Hold Acknowledge. HoldAck outputs a logic 1 when the 403GCX
relinquishes its external buses to an external bus master. HoldAck
outputs a logic 0 when the 403GCX regains control of the bus.
HoldReq
14
F2
I
Hold Request. External bus masters can request the 403GCX bus
by placing a logic1 on this pin. The external bus master relinquishes
the bus to the 403GCX by deasserting HoldReq.
INT0
31
K3
I
Interrupt 0. INT0 is an interrupt input to the 403GCX and users may
program the pin to be either edge-triggered or level-triggered and
may also program the polarity to be active high or active low. The
IOCR contains the bits necessary to program the trigger type and
polarity.
INT1
32
K2
I
Interrupt 1. See description of INT0.
INT2
33
K4
I
Interrupt 2. See description of INT0.
INT3
34
L1
I
Interrupt 3. See description of INT0.
INT4
35
L3
I
Interrupt 4. See description of INT0.
IVR
39
M2
I
Reserved for manufacturing test. Tied high for normal operation.
OE/XSize1/
BLast
126
B11
O/I/O
Output Enable / External Master Transfer Size 1. When the 403GCX
is bus master, OE enables the selected SRAMs to drive the data
bus. The timing parameters of OE relative to the chip select, CS,
are programmable via bits in the 403GCX bank registers.
When the 403GCX is not bus master, OE/XSize1 is used as one of
two external transfer size input bits, XSize0:1.
In Byte Enable mode, Burst Last (BLast) goes active to indicate the
last transfer of a memory access, whether burst or nonburst.
Ready
13
E4
I
Ready. Ready is used to insert externally generated (device-paced)
wait states into bus transactions. The Ready pin is enabled via the
Ready Enable bit in 403GCX bank registers.
RecvD
27
J3
I
Serial Port Receive Data.
Table 4. 403GCX Signal Descriptions
Signal
Name
Pin
Ball
I/O
Type
Function
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