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参数资料
| 型号： | IBM25403GCX-3JC76C2 |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | RISC PROCESSOR, PQFP16 |
| 封装： | PLASTIC, QFP-160 |
| 文件页数： | 54/54页 |
| 文件大小： | 541K |
| 代理商： | IBM25403GCX-3JC76C2 |
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IBM PowerPC 403GCX
9
A29
119
C13
I/O
Address Bus Bit 29. See description of A22.
AMuxCAS
139
A8
O
DRAM External Address Multiplexer Select. AMuxCAS controls the
select logic on an external multiplexer. If AMuxCAS is low, the multi-
plexer should select the row address for the DRAM and when
AMuxCAS is 1, the multiplexer should select the column address.
BootW
11
E1
I
Boot-up ROM Width Select. BootW is sampled while the Reset pin
is active and again after Reset becomes inactive to determine the
width of the boot-up ROM. If this pin is tied to logic 0 when sampled
on reset, an 8-bit boot width is assumed. If BootW is tied to 1, a 32-
bit boot width is assumed. For 16-bit boot widths, this pin should be
tied to the RESET pin.
BusError
12
E3
I
Bus Error Input. A logic 0 input to the BusError pin by an external
device signals to the 403GCX that an error occurred on the bus
transaction. BusError is only sampled during the data transfer cycle
or the last wait cycle of the transfer.
BusReq/
DMADXFER
135
A9
O
Bus Request. While HoldAck is active, BusReq is active when the
403GCX has a bus operation pending and needs to regain control
of the bus.
DMA Data Transfer. When HoldAck is not active, DMADXFER indi-
cates a valid data transfer cycle. For DMA use, DMADXFER con-
trols burst-mode y-by DMA transfers between memory and
peripherals. DMADXFER is not meaningful unless a DMA Acknowl-
edge signal (DMAA0:3) is active. For transfer rates slower than one
transfer per cycle, DMADXFER is active for one cycle when one
transfer is complete and the next one starts. For transfer rates of
one transfer per cycle, DMADXFER remains active throughout the
transfer.
CAS0
142
C8
O
DRAM Column Address Select 0. CAS0 is used with byte 0 of all
DRAM banks.
CAS1
143
A7
O
DRAM Column Address Select 1. CAS1 is used with byte 1 of all
DRAM banks.
CAS2
144
B7
O
DRAM Column Address Select 2. CAS2 is used with byte 2 of all
DRAM banks.
CAS3
145
D7
O
DRAM Column Address Select 3. CAS3 is used with byte 3 of all
DRAM banks.
CINT
36
L2
I
Critical Interrupt. To initiate a critical interrupt, the user must main-
tain a logic 0 on the CINT pin for a minimum of one SysClk clock
cycle followed by a logic 1 on the CINT pin for at least one SysClk
cycle.
CS0
155
C4
O
SRAM Chip Select 0. Bank register 0 controls an SRAM bank, CS0
is the chip select for that bank.
CS1
154
A4
O
SRAM Chip Select 1. See description of CS0 but controls bank 1.
Table 4. 403GCX Signal Descriptions
Signal
Name
Pin
Ball
I/O
Type
Function
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