参数资料
型号: IBM25PPC405GP-3DE266CZ
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 266.66 MHz, RISC PROCESSOR, PBGA456
封装: 27 X 27 MM, ENHANCED, PLASTIC, BGA-456
文件页数: 51/60页
文件大小: 1480K
代理商: IBM25PPC405GP-3DE266CZ
PowerPC 405GP Embedded Processor Data Sheet
6/20/03
Page 55 of 60
I/O Specifications—266MHz
Notes:
1. The SDRAM command interface is configurable through SDRAM0_TR[LDF] to provide a 2 to 4 cycle delay before the
command is used by SDRAM.
2. SDRAM I/O timings are specified relative to a MemClkOut terminated into a lumped 10pF load.
3. SDRAM interface hold times are guaranteed at the PPC405GP package pin. System designers must use the
PPC405GP IBIS model (available from www.chips.ibm.com) to ensure their clock distribution topology minimizes
loading and reflections, and that the relative delays on clock wiring do not exceed the delays on other SDRAM signal
wiring.
4. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns.
5. I/O H is specified at 2.4 V and I/O L is specified at 0.4 V.
Signal
Input (ns)
Output (ns)
Output Current (mA)
Clock
Notes
Setup Time
(TIS min)
Hold Time
(TIH min)
Valid Delay
(TOV max)
Hold Time
(TOH min)
I/O H
(maximum)
I/O L
(minimum)
SDRAM Interface
BA1:0
na
5.7
1
19
12
MemClkOut
1, 2
BankSel3:0
na
4.8
1
19
12
MemClkOut
2
CAS
na
5.7
1
19
12
MemClkOut
1, 2
ClkEn0:1
na
4.2
1
40
25
MemClkOut
2
DQM0:3
na
4.8
1
19
12
MemClkOut
2
DQMCB
na
4.8
1
19
12
MemClkOut
2
ECC0:7
1.5
1
4.8
1
19
12
MemClkOut
2
MemAddr12:0
na
5.7
1
19
12
MemClkOut
1, 2
MemData0:31
1.5
1
4.9
1
19
12
MemClkOut
2
RAS
na
5.7
1
19
12
MemClkOut
1, 2
WE
na
5.7
1
19
12
MemClkOut
1, 2
External Slave Peripheral Interface
DMAAck0:3
na
6
0
12
8
PerClk
DMAReq0:3
4
1
na
PerClk
EOT0:3/TC0:3
dc
6
0
12
8
PerClk
PerAddr0:31
3
1
7.2
0
19
12
PerClk
PerBLast
3
1
6
0
12
8
PerClk
PerCS0
PerCS1:7[GPIO10:16]
na
6
0128
PerClk
PerData0:31
5
1
7.2
0
19
12
PerClk
PerOE
na
6
0128
PerClk
PerPar0:3
3
1
7.2
0
19
12
PerClk
PerR/W
4
1
6
0
12
8
PerClk
PerReady
6.5
1
na
PerClk
PerWBE0:3
3
1
6
0
12
8
PerClk
External Master Peripheral Interface
BusReq
na
6
0128
PerClk
ExtAck
na
6
0128
PerClk
ExtReq
4
1
nana
PerClk
ExtReset
na
6
0
19
12
PerClk
HoldAck
na
6
0
12
8
PerClk
HoldPri
3
1
na
PerClk
HoldReq
4
1
na
PerClk
na
0.9
0.7
19
12
PLB Clk
4
PerErr
3
1
na
PerClk
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