参数资料
型号: ICS527R-01T
元件分类: 时钟及定时
英文描述: 527 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28
封装: 0.150 INCH, 0.025 INCH PITCH, MO-153, SSOP-28
文件页数: 1/9页
文件大小: 176K
代理商: ICS527R-01T
ICS527-01
MDS 527-01 E
1
Revision 032405
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com
Clock Slicer User Configurable Zero Delay Buffer
Description
The ICS527-01 Clock Slicer is the most flexible way to
generate an output clock from an input clock with zero
skew. The user can easily configure the device to
produce nearly any output clock that is multiplied or
divided from the input clock. The part supports
non-integer multiplications and divisions. A SYNC
pulse indicates when the rising clock edges are aligned
with zero skew. Using Phase-Locked Loop (PLL)
techniques, the device accepts an input clock up to 200
MHz and produces an output clock up to 160 MHz.
The ICS527-01 aligns rising edges on ICLK and FBIN
at a ratio determined by the reference and feedback
dividers.
For configurable clocks that do not require zero delay,
use the ICS525.
Features
Packaged as 28-pin SSOP (150 mil body)
Synchronizes fractional clocks rising edges
Pin configurable multiplication/division ratio
Slices frequency or period
SYNC pulse output indicates aligned edges
Input clock frequency of 600 kHz to 200 MHz
Output clock frequencies up to 160 MHz
Very low jitter
Duty cycle of 45/55 up to 160 MHz
Operating voltage of 3.3V
Pin selectable drive strength
Multiple outputs available when combined with
fanout buffers
Industrial temperature version available
Available in Pb (lead) free package
Block Diagram
ICLK
2xDRIVE
CLK1
CLK2
Reference
Divider
PLL
7
72
R6:R0
F6:F0
S1:S0
PDTS
Feedback
Divider
FBIN
1
0
Divide
by 2
SYNC
DIV2
Feedback can
come from
CLK1 or CLK2
(not both)
PDTS
OECLK2
PDTS
2
GND
2
VDD
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