- 您现在的位置：买卖IC网 > PDF目录261237 > ICS527R-01T 527 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 PDF资料下载
参数资料
| 型号： | ICS527R-01T |
| 元件分类： | 时钟及定时 |
| 英文描述： | 527 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 封装： | 0.150 INCH, 0.025 INCH PITCH, MO-153, SSOP-28 |
| 文件页数： | 4/9页 |
| 文件大小： | 176K |
| 代理商： | ICS527R-01T |
Clock Slicer User Configurable Zero Delay Buffer
MDS 527-01 E
4
Revision 032405
Integrated Circuit Systems, Inc.
● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS527-01
FB Frequency is the same as either CLK1 or
CLK2 depending on feedback connection
Also, the following operating ranges should be
observed:
S1 and S0 should be set for the frequency of CLK1,
according to the Frequency Range Table on page
2. The device can be operated below the lower
limits stated in table 2, however, jitter and skew may
be higher. Therefore, if your expected output
frequency covers more than one frequency range,
use the setting for the highest frequency expected.
The dividers are expressed as integers. For example, if
a 50 MHz output on CLK1 is desired from a 40 MHz
input, the reference divider word (RDW) should be 2
and the feedback divider word (FDW) should be 3
which gives the required 5/4 multiplication. Then R6:R0
is 0000010, F6:F0 is 0000011 and S1:S0 is 00. Also,
this example assumes CLK1 is connected to
FBIN.S1:S0 is set by referring to the Frequency Range
Table. The setting for 50 MHz is 00.
For assistance with configuring the device, please send
a description of your requirements using the “Technical
Support” link at www.icst.com.
Typical Example
The following connection diagram shows the implementation of the example from the previous section.
This will generate a 50 MHz clock synchronously with a 40 MHz input. A SYNC pulse is desired and the 1x
output drive is selected.T
Note: The series termination resistor is located before the feedback trace.
300kHz
Input Frequency
RDW
2
+
-------------------------------------------
<
F6
ICLK
F5
F4
GND
F3
OECLK2
2XDRIVE
F0
F1
F2
CLK1
CLK2
GND
S1
VDD
R0
VDD
DIV2
S0
R2
R1
R5
R6
R4
R3
FBIN
PDTS
50 MHz
SYNC
33
0.01 F
40 MHz
0.01 F
VDD
相关PDF资料 |
PDF描述 |
|---|---|
| IDT74FCT2541CTD | FCT SERIES, 8-BIT DRIVER, TRUE OUTPUT, CDIP20 |
| IDTQS3LR384SO8 | DUAL 5-BIT DRIVER, TRUE OUTPUT, PDSO24 |
| IDT74LVCH646APG | LVC/LCX/Z SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24 |
| IDT74LVCH646ASO | LVC/LCX/Z SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24 |
| IDT74FCT540ATPY | FCT SERIES, 8-BIT DRIVER, INVERTED OUTPUT, PDSO20 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS527R-02 | 功能描述:IC CLOCK SLICER ZD BUFFER 28SSOP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 产品变化通告:Product Discontinuation 04/May/2011 标准包装:96 系列:- 类型:时钟倍频器，零延迟缓冲器 PLL:带旁路 输入:LVTTL 输出:LVTTL 电路数:1 比率 - 输入:输出:1:8 差分 - 输入:输出:无/无 频率 - 最大:133.3MHz 除法器/乘法器:是/无 电源电压:3 V ~ 3.6 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:管件 其它名称:23S08-5HPGG |
| ICS527R-02I | 功能描述:IC CLOCK SLICER ZD BUFFER 28SSOP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:1,000 系列:- 类型:时钟/频率合成器，扇出分配 PLL:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 除法器/乘法器:- 电源电压:- 工作温度:- 安装类型:表面贴装 封装/外壳:56-VFQFN 裸露焊盘 供应商设备封装:56-VFQFP-EP（8x8） 包装:带卷 (TR) 其它名称:844S012AKI-01LFT |
| ICS527R-02ILF | 制造商:Integrated Device Technology Inc 功能描述:IC CLOCK SLICER ZD BUFFER 28SSOP |
| ICS527R-02ILFT | 制造商:Integrated Device Technology Inc 功能描述:IC CLOCK SLICER ZD BUFFER 28SSOP |
| ICS527R-02IT | 功能描述:IC CLOCK SLICER ZD BUFFER 28SSOP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:1,000 系列:- 类型:时钟/频率合成器，扇出分配 PLL:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 除法器/乘法器:- 电源电压:- 工作温度:- 安装类型:表面贴装 封装/外壳:56-VFQFN 裸露焊盘 供应商设备封装:56-VFQFP-EP（8x8） 包装:带卷 (TR) 其它名称:844S012AKI-01LFT |
发布紧急采购，3分钟左右您将得到回复。