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参数资料
| 型号： | ICS9148F-11 |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 66.6 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | SSOP-48 |
| 文件页数： | 10/14页 |
| 文件大小： | 559K |
| 代理商： | ICS9148F-11 |
5
ICS9148-11
Serial Configuration Command Bitmaps
Byte 0: Functional and Frequency Select Clock Register (Default=0)
General I2C serial interface information
BIT
PIN#
DESCRIPTION
PWD
Bit 7
-
Reserved
0
Bit 6
-
Must be 0 for normal operation
0
Bit 5
-
Must be 0 for normal operation
0
In Spread Spectrum, Controls type
(0=centered, 1=down spread)
0
Bit 4
-
Must be 0 for normal operation
0
In Spread Spectrum, Controls Spreading
(0=1.8%, 1=0.6%)
0
Bit 3
-
Reserved
0
Bit 2
-
Reserved
0
Bit 1
Bit 0
-
Bit1
1
0
Bit0
1 - Tri-State
0 - Spread Spectrum Enable
1 - Testmode
0 - Normal operation
0
Note: PWD = Power-Up Default
A.
For the clock generator to be addressed by an I2C controller, the following address must be sent as a start sequence,
with an acknowledge bit between each byte.
B.
The clock generator is a slave/receiver I2C component. It can "read back "(in Philips I2C protocol) the data stored in the
latches for verification. (set R/W# to 1 above). There is no BYTE count supported, so it does not meet the Intel SMB
PIIX4 protocol.
C.
The data transfer rate supported by this clock generator is 100K bits/sec (standard mode)
D.
The input is operating at 3.3V logic levels.
E.
The data byte format is 8 bit bytes.
F.
To simplify the clock generator I2C interface, the protocol is set to use only block writes from the controller. The bytes
must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has
been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two
bytes. The data is loaded until a Stop sequence is issued.
G.
In the power down mode (PWR_DWN# Low), the SDATA and SCLK pins are tristated and the internal data latches
maintain all prior programming information.
H.
At power-on, all registers are set to a default condition. See Byte 0 detail for default condition, Bytes 1 through 5 default
to a 1 (Enabled output state)
Then Byte 0, 1, 2, etc in
sequence until STOP.
Byte 0, 1, 2, etc in sequence until STOP.
Clock Generator
Address (7 bits)
ACK
+ 8 bits dummy
command code
ACK
+ 8 bits dummy
Byte count
ACK
A(6:0) & R/W#
D2(H)
Clock Generator
Address (7 bits)
ACK
Byte 0
ACK
Byte 1
ACK
A(6:0) & R/W#
D3(H)
相关PDF资料 |
PDF描述 |
|---|---|
| ICS9148F-14LF | 66.6 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| ICS9148F-14 | 66.6 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| ICS9148F-14LF | 66.6 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| ICS9148F-14 | 66.6 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| ICS9148F-17-LF | 100.3569 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS9148F-12 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:CPU System Clock Generator |
| ICS9148F-13 | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Generator & Integrated Buffers for PENTIUMTM |
| ICS9148F-13T | 制造商:ICS 功能描述:9148F-13T |
| ICS9148F-17 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:CPU System Clock Generator |
| ICS9148F-18 | 制造商:ICS 制造商全称:ICS 功能描述:Pentium/ProTM System Clock Chip |
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