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参数资料
| 型号： | ICS9148F-11 |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 66.6 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | SSOP-48 |
| 文件页数： | 12/14页 |
| 文件大小： | 559K |
| 代理商： | ICS9148F-11 |
7
ICS9148-11
Power Management
ICS9148-11 Power Management Requirements
Clock Enable Configuration
Fullclockcycletimingisguaranteedatalltimesafterthesystemhasinitiallypoweredupexceptwherenoted.Thefirstclockpulsecomingout
of a stopped clock condition may be slightly distorted due to clock network chargingcircuitry. Board routing and signal loading may have a
large impact on the initial clock distortion also.
Notes.
1. Clock on latency is defined from when the clock enable goes active to when the first valid clock comes out of the device.
2. Clock off latency is defined from when the clock enable goes inactive to when the last clock is driven low out of the device.
3. Power up latency is when PD# goes inactive (high) to when the first valid clocks are output by the device.
4. Power down has controlled clock counts applicable to CPUCLK, SDRAM, PCICLK only.
The REF and IOAPIC will be stopped independant of these.
SIGNAL
SIGNAL STATE
Latency
No. of rising edges of free
running PCICLK
CPU_ STOP#
0 (Disabled)
2
1
1 (Enabled)
1
PCI_STOP#
0 (Disabled)
2
1
1 (Enabled)
1
PWR_DWN#
1 (Normal Operation)
3
3mS
0 (Power Down)
4
2max
Byte 5: Peripheral Clock Register
Notes: 1 = Enabled; 0 = Disabled, outputs held low
BIT
PIN#
PWD
DESCRIPTION
Bit 7
-
1
Reserved
Bit 6
-
1
Reserved
Bit 5
46
1
IOAPIC1 (Act/Inact)
Bit 4
47
1
IOAPIC0 (Act/Inact)
Bit 3
-
1
Reserved
Bit 2
-
1
Reserved
Bit 1
-
1
Reserved
Bit 0
2
1
REF0(Act/Inact)
CPU_STOP#
PCI_STOP#
PWR_DWN#
CPUCLK
PCICLK
Other Clocks,
SDRAM,
REF,
IOAPICs
Crystal
VCOs
X
0
Low
Stopped
Off
0
1
Low
Running
0
1
Low
33.3 MHz
Running
1
0
1
66.6 MHz
Low
Running
1
66.6 MHz
33.3 MHz
Running
Byte 6: Optional Register for Future
Notes:
1. Byte 6 is reserved by Integrated Circuit Systems for
future applications.
BIT
PIN#
PWD
DESCRIPTION
Bit 7
-
1
Reserved
Bit 6
-
1
Reserved
Bit 5
-
1
Reserved
Bit 4
-
1
Reserved
Bit 3
-
1
Reserved
Bit 2
-1
Reserved
Bit 1
-
1
Reserved
Bit 0
-
1
Reserved
Note: PWD = Power-Up Default
相关PDF资料 |
PDF描述 |
|---|---|
| ICS9148F-14LF | 66.6 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| ICS9148F-14 | 66.6 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| ICS9148F-14LF | 66.6 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| ICS9148F-14 | 66.6 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| ICS9148F-17-LF | 100.3569 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS9148F-12 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:CPU System Clock Generator |
| ICS9148F-13 | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Generator & Integrated Buffers for PENTIUMTM |
| ICS9148F-13T | 制造商:ICS 功能描述:9148F-13T |
| ICS9148F-17 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:CPU System Clock Generator |
| ICS9148F-18 | 制造商:ICS 制造商全称:ICS 功能描述:Pentium/ProTM System Clock Chip |
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