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参数资料
| 型号： | ICS9148F-11 |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 66.6 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | SSOP-48 |
| 文件页数： | 9/14页 |
| 文件大小： | 559K |
| 代理商： | ICS9148F-11 |
4
ICS9148-11
VDD(1,2,3)
Thisisthepowersupplytotheinternalcorelogicofthedeviceaswell
as the clock output buffers for REF(0:1), PCICLK, 48/24MHzA/B
and SDRAM(0:7).
Thispinoperatesat3.3Vvolts.Clocksfromthelistedbuffersthatit
supplieswillhaveavoltageswingfromGroundtothislevel. Forthe
actualguaranteedhighandlowvoltagelevelsfortheClocks,please
consult the DC parameter table in this data sheet.
VDDL1,2
This is the power supplies for the CPUCLK and IOAPCI output
buffers. The voltage level for these outputs may be 2.5 or 3.3volts.
Clocksfromthebuffersthateachsupplieswillhaveavoltageswing
from Ground to this level. For the actual Guaranteed high and low
voltage levels of these Clocks, please consult the DC parameter
table in this Data Sheet.
GND
Thisisthepowersupplyground(commonornegative)returnpinfor
the internal core logic and all the output buffers.
X1
Thisinputpinservesoneoftwofunctions. Whenthedeviceisused
with a Crystal, X1 acts as the input pin for the reference signal that
comes from the discrete crystal. When the device is driven by an
external clock signal, X1 is the device input pin for that reference
clock. ThispinalsoimplementsaninternalCrystalloadingcapacitor
that is connected to ground. With a nominal value fo 33pF no
external load cap is needed for a CL=17 to 18pF crystal.
X2
This Output pin is used only when the device uses a Crystal as the
reference frequency source. In this mode of operation, X2 is an
outputsignalthatdrives(orexcites)thediscreteCrystal. TheX2pin
willalsoimplementaninternalCrystalloadingcapacitornominally
33pF.
CPUCLK (0:3)
These Output pins are the Clock Outputs that drive processor and
other CPU related circuitry that requires clocks which are in tight
skew tolerance with the CPU clock. The voltage swing of these
ClocksarecontrolledbytheVoltagelevelappliedtotheVDDL2pin
of the device. See the FunctionalityTable for a list of the specific
frequencies that are available for these Clocks and the selection
codes to produce them.
SDRAM(0:11)
These Output Clocks are use to drive Dynamic RAMs and are low
skew copies of the CPU Clocks. The voltage swing of the
SDRAMs output is controlled by the supply voltage that is applied
to VDD3 of the device, operates at 3.3 volts.
IOAPIC (0:1)
This Output is a fixed frequency Output Clock that runs at the
Reference Input (typically 14.31818MHz) . Its voltage level swing
is controlled by VDDL1 and may operate at 2.5 or 3.3volts.
Technical Pin Function Descriptions
REF0
The REF Output is a fixed frequency Clock that runs at the same
frequency as the Input Reference Clock X1 or the Crystal (typically
14.31818MHz) attached across X1 and X2.
PCICLK_F
This Output is equal to PCICLK(0:5) and is FREE RUNNING, and
will not be stopped by PCI_STP#.
PCICLK (0:5)
These Output Clocks generate all the PCI timing requirements for a
Pentium/Pro based system. They conform to the current PCI
specification.They run at 1/2 CPU frequency.
MODE
ThisInputpinisusedtoselecttheInputfunctionofthe I/Opins. An
activeLowwillplacetheI/OpinsintheInputmodeandenablethose
stop clock functions.
PWR_DWN#
This is an asynchronous active Low Input pin used to Power Down
thedeviceintoaLowPowerstatebynotremovingthepowersupply.
The internal Clocks are disabled and the VCO and Crystal are
stopped. PoweredDownwillalsoplacealltheOutputsinalowstate
attheendoftheircurrentcycle. ThelatencyofPowerDownwillnot
be greater than 3ms. The I2CinputswillbeTri-Statedandthedevice
willretainallprogramminginformation.Thisinputpinonlyvalidwhen
MODE=0 (Power Management Mode)
CPU_STOP#
This is a synchronous active Low Input pin used to stop the
CPUCLK clocks in an active low state. All other Clocks including
SDRAM clocks will continue to run while this function is enabled.
The CPUCLKs will have a turn ON latency of at least 3 CPU
clocks.ThisinputpinonlyvalidwhenMODE=0(PowerManagement
Mode)
PCI_STOP#
ThisisasynchronousactiveLowInputpinusedtostopthePCICLK
clocks in an active low state. It will not effect PCICLK_F nor any
other outputs. This input pin only valid when MODE=0 (Power
Management Mode)
I2C
The SDATAand SCLOCK Inputs are use to program the device.
The clock generator is a slave-receiver device in the I2C protocol.
It will allow read-back of the registers. See configuration map for
register functions. The I2C specification in Philips I2C Peripherals
Data Handbook (1996) should be followed.
OE
Output Enable tristates the outputs when held low. This pin will
override the I2C Byte 0 function, so that the outputs will be tristated
whentheOEislowregardlessoftheI2Cdefinedfunction.WhenOE
is high, the I2C function is in active control.
相关PDF资料 |
PDF描述 |
|---|---|
| ICS9148F-14LF | 66.6 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| ICS9148F-14 | 66.6 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| ICS9148F-14LF | 66.6 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| ICS9148F-14 | 66.6 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| ICS9148F-17-LF | 100.3569 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS9148F-12 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:CPU System Clock Generator |
| ICS9148F-13 | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Generator & Integrated Buffers for PENTIUMTM |
| ICS9148F-13T | 制造商:ICS 功能描述:9148F-13T |
| ICS9148F-17 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:CPU System Clock Generator |
| ICS9148F-18 | 制造商:ICS 制造商全称:ICS 功能描述:Pentium/ProTM System Clock Chip |
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