参数资料
型号: ICS9148F-11
元件分类: 时钟产生/分配
英文描述: 66.6 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
封装: SSOP-48
文件页数: 13/14页
文件大小: 559K
代理商: ICS9148F-11
8
ICS9148-11
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9148-11. It is used to turn off the PCICLK (0:5) clocks for low power operation.
PCI_STOP# is synchronized by theICS9148-11internally.TheminimumthatthePCICLK(0:5)clocksareenabled(PCI_STOP#highpulse)
is at least 10 PCICLK (0:5) clocks. PCICLK (0:5) clocks are stopped in a low state and started with a full high pulse width guaranteed.
PCICLK (0:5) clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
CPU_STOP# Timing Diagram
CPUSTOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation. CPU_STOP#
is synchronized by theICS9148-11.TheminimumthattheCPUCLKisenabled(CPU_STOP#highpulse)is100CPUCLKs.Allotherclocks
will continue to run while the CPUCLKs are disabled. The CPUCLKs will always be stopped in a low state and start in such a manner that
guaranteesthehighpulsewidthisafullpulse.CPUCLKonlatencyislessthan4CPUCLKsandCPUCLKofflatencyislessthan4CPUCLKs.
(Drawing shown on next page.)
Notes:
1. All timing is referenced to the internal CPUCLK.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPUCLKs inside
the ICS9148-11.
3. All other clocks continue to run undisturbed.
4. PD# and PCI_STOP# are shown in a high (true) state.
相关PDF资料
PDF描述
ICS9148F-14LF 66.6 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
ICS9148F-14 66.6 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
ICS9148F-14LF 66.6 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
ICS9148F-14 66.6 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
ICS9148F-17-LF 100.3569 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
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