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参数资料
| 型号： | ICS9148F-14LF |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 66.6 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | 0.300 INCH, SSOP-48 |
| 文件页数： | 14/18页 |
| 文件大小： | 807K |
| 代理商： | ICS9148F-14LF |
5
ICS9148-14
value is present on this pin, the 66.6 MHz Clock will be
selected at power_on. If a logic 0 is used, the 100MHz
frequency will be selected at power_on.
MODE
This Input pin is used to select the Input function of the I/O
pins. An active Low will place the I/O pins in the Input mode
and enable those stop clock functions (no pullup).
CPU 3.3_2.5#
This Input pin controls the CPU output buffer strength for
skew matching CPU and SDRAM outputs to compensate for
the external VDDL supply condition. It is important to use
this function when selecting power supply requirements for
VDDL.A logic 0 (ground) will indicate 2.5V operation and
a logic 1 will indicate 3.3V operation.
PWR_DWN#
This is an asynchronous active Low Input pin used to Power
Down the device into a Low Power state by not removing the
power supply. The internal Clocks are disabled and theVCO
and Crystal are stopped. Powered Down will also place all
the Outputs in a low state at the end of their current cycle.
The latency of Power Down will not be greater than 3ms back
to operating speed if the spread spectrum is disabled (normal
mode). With spread spectrum enabled, the power up transition
may have more variability in CPU speed, with final setting by
10ms. By keeping the CPU_STOP# and PCI_STOP# pins low
for this 10ms interval after PWR_DWN# goes high (out of
standby), there will be only full speed clocks seen where the
Stop Clock signals are brought high. The I2C inputs will be
Tri-Stated and the device will retain all programming
information. This input is always available (independent of
MODE state).
CPU_STOP#
This is a synchronous active Low Input pin used to stop the
CPUCLK in an active low state. All other Clocks including
SDRAM clocks will continue to run while this function is
enabled if the PCI_STOP# is High. If both CPU_STOP# and
PCI_STOP# are Low, then the SDRAM clocks are also
stopped low. The CPUCLKs will have a turn ON latency of at
least 3 CPU clocks. This input pin only valid when MODE=0
(Power Management Mode)
PCI_STOP#
This is a synchronous active Low Input pin used to stop the
AGP, PCICLK and E_PCICLK clocks in an active low state. It
will not effect any outputs if CPU_STOP# is high. This input
pin only valid when MODE=0 (Power Management Mode)
I2C
The SDATA and SCLOCK Inputs are used to program the
device. The clock generator is a slave-receiver device in the
I2C protocol. It will allow read-back of the registers. See
Technical Pin Function Descriptions
configuration map for register functions. The I2C specification
in Philips I2C Peripherals Data Handbook (1996) should be
followed. These pins are 5V logic input tolerant.
相关PDF资料 |
PDF描述 |
|---|---|
| ICS9148F-14 | 66.6 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| ICS9148F-17-LF | 100.3569 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| ICS9148F-17 | 100.3569 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| ICS9148F-18LF | 100 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28 |
| ICS9148F-25 | 83.3 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS9148F-17 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:CPU System Clock Generator |
| ICS9148F-18 | 制造商:ICS 制造商全称:ICS 功能描述:Pentium/ProTM System Clock Chip |
| ICS9148F-20 | 制造商:ICS 制造商全称:ICS 功能描述:Pentium/ProTM System Clock Chip |
| ICS9148F25 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Industrial Control IC |
| ICS9148F-25 | 功能描述:IC CLK SYNTHESIZER CHIP 48-SSOP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:28 系列:- 类型:时钟/频率发生器 PLL:是 主要目的:Intel CPU 服务器 输入:时钟 输出:LVCMOS 电路数:1 比率 - 输入:输出:3:22 差分 - 输入:输出:无/是 频率 - 最大:400MHz 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:64-TFSOP （0.240"，6.10mm 宽） 供应商设备封装:64-TSSOP 包装:管件 |
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