参数资料
型号: ICS9148F-14LF
元件分类: 时钟产生/分配
英文描述: 66.6 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
封装: 0.300 INCH, SSOP-48
文件页数: 4/18页
文件大小: 807K
代理商: ICS9148F-14LF
12
ICS9148-14
PWR_DWN# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is
an asynchronous active low input. This signal is synchronized internal by the ICS9148-14 prior to its control action of
powering down the clock synthesizer. Internal clocks will not be running after the device is put in power down state.When PD#
is active (low) all clocks are driven to a low state and held prior to turning off theVCOs and the Crystal oscillator. The power on
latency is guaranteed to be less than 3mS. The power down latency is less than three CPUCLK cycles. PCI_STOP# and
CPU_STOP# are dont care signals during the power down operations.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9148 device).
2. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside the ICS9148.
3. The shaded sections on the VCO and the Crystal signals indicate an active clock is being generated.
4. Power up latency is when PD# goes inactive (high) to when the first valid clocks are output by the device. This delay is only valid in
normal (not spread spectrum) mode. Power-up from spread spectrum mode requires 10ms for valid clocks, it is recommended to keep
CPU_STOP# and PCI_STOP# low coming out of PD Low for this interval.
相关PDF资料
PDF描述
ICS9148F-14 66.6 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
ICS9148F-17-LF 100.3569 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
ICS9148F-17 100.3569 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
ICS9148F-18LF 100 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28
ICS9148F-25 83.3 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
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