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参数资料
| 型号： | ICS9342YF-PPP-T |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 146.62 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | 0.300 INCH, SSOP-48 |
| 文件页数： | 10/10页 |
| 文件大小： | 175K |
| 代理商： | ICS9342YF-PPP-T |
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ICS9342
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PCI_STOP# Timing Diagram
PCI_STOP# is an input to the clock synthesizer. It is used to turn off the PCIREF clock for low power operation. PCIREF clock
is required to be stopped in a low state and started such that a full high pulse width is guaranteed.
Notes:
1. All timing is referenced to CPUCLK.
2. Internal means inside the chip.
3. All other clocks continue to run undisturbed.
4. PD# and CPU_STOP# are shown in a high state.
CPUCLK
(internal)
(externall)
PCICLK
PCI_STOP#
CPU_STOP#
PD#
PCIREF
CPU_STOP# Timing Diagram
CPU_STOP# is an asynchronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation.
CPU_STOP# is asserted asynchronously by the external clock control logic with the rising edge of free running PCI clock
(and hence CPU clock) and must be internally synchronized to the external output. All other clocks will continue to run while
the CPU clocks are disabled. The CPU clocks must always be stopped in a low state and started in such a manner as to
guarantee that the high pulse width is a full pulse.
Notes:
1. All timing is referenced to the internal CPUCLK.
2. The internal label means inside the chip and is a reference only. This in fact may not be the way that the control is designed.
3. PD# and PCI_STOP# are shown in a high state.
CPUCLK
(internal)
(externall)
PCICLK
PCI_STOP#
CPU_STOP#
PD#
CPUCLK
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS9342YF-T | 制造商:ICS 制造商全称:ICS 功能描述:133MHz Clock Generator and Integrated Buffer for PowerPC⑩ |
| ICS93701 | 制造商:ICS 制造商全称:ICS 功能描述:DDR Phase Lock Loop Clock Driver |
| ICS93701YGT | 制造商:ICS 制造商全称:ICS 功能描述:DDR Phase Lock Loop Clock Driver |
| ICS93705 | 制造商:ICS 制造商全称:ICS 功能描述:DDR Phase Lock Loop Zero Delay Clock Buffer |
| ICS93705YF-T | 制造商:ICS 制造商全称:ICS 功能描述:DDR Phase Lock Loop Zero Delay Clock Buffer |
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