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参数资料
| 型号： | ICS9342YF-PPP-T |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 146.62 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | 0.300 INCH, SSOP-48 |
| 文件页数： | 3/10页 |
| 文件大小： | 175K |
| 代理商： | ICS9342YF-PPP-T |
2
ICS9342
Third party brands and names are the property of their respective owners.
Pin Configuration
General Description
The ICS9342 generates all clocks required for high speed PowerPC RISC microprocessor systems. With a zero delay buffer
chip such as the ICS9112-17 multiple PCI clock outputs can be generated in phase with PCIREF.
Spread Spectrum may be enabled by driving the SS_EN# pin low. Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9342
employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature
variations.
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
1
VDDREF
PWR
Ref(1:0), XTAL power supply, nominal 3.3V
2,3
REF[1:0]
OU T
14.318 M Hz reference clocks
4
GNDREF
PWR
Ground pin for the REF outputs
5
X1
IN
Crystal input,nominally 14.318M Hz.
6
X2
OU T
Crystal output, nominally 14.318M Hz.
7
PD#
IN
Pow ers down chip, active low .
8
CPU_STOP#
IN
Stops all CPUCLKs [11:0] at logic 0 level, w hen input low
9
VDD
PWR
3.3V power for the digital core.
10
GND
PWR
Ground pin for the digital core.
11
PCI_STO P#
IN
Drives PCIREF to logic 0 level, when input low
12
SS_EN#
IN
Spread spectrum is turned on by driving this input low and turned off by
driving it high.
13
VDDPCI
PWR
Pow er supply for PCIREF, nominal 3.3V.
14
PCIREF
OU T
Reference clock for PCI Zero Delay Buffer.
15
GNDPCI
PWR
Ground pin for PCIREF.
18, 17, 16
FS (2:0)
IN
Frequency select pins.
19
VDDFP
PWR
3.3V power for the Fixed PLL core.
20
GNDFP
PER
Ground pin for the Fixed PLL core.
OUT
3.3V OUT reference clock.
TEST#
IN
Logic input to select over clocking or under clocking frequencies.
(latched input)
OUT_D IV2
OU T
3.3V 1/2 frequency OUT reference clock.
BOOST#
IN
Logic input to select normal or test mode frequencies. (latched input)
23
PDFP#
IN
Pow ers down Fixed PLL. When driven to low, OUT and OUT_DIV2 clocks
will be stopped
24
VDDA
PWR
3.3V power for the PLL core
48, 25
OUTSEL(1:0)
IN
Frequency select pins for OUT and OUT_DIV2 clocks.
26, 31, 36, 41, 46
GNDCPU
PWR
Ground pin for CPU clocks.
27, 32, 37, 42, 47
VDDCPU
PWR
3.3V power supply for CPU clocks.
21
22
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PDF描述 |
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| ICS93712YF-T | LOW SKEW CLOCK DRIVER, 6 TRUE OUTPUT(S), 6 INVERTED OUTPUT(S), PDSO28 |
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| ICS93776YFLF-T | 93776 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| ICS95V157YGLF | PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS9342YF-T | 制造商:ICS 制造商全称:ICS 功能描述:133MHz Clock Generator and Integrated Buffer for PowerPC⑩ |
| ICS93701 | 制造商:ICS 制造商全称:ICS 功能描述:DDR Phase Lock Loop Clock Driver |
| ICS93701YGT | 制造商:ICS 制造商全称:ICS 功能描述:DDR Phase Lock Loop Clock Driver |
| ICS93705 | 制造商:ICS 制造商全称:ICS 功能描述:DDR Phase Lock Loop Zero Delay Clock Buffer |
| ICS93705YF-T | 制造商:ICS 制造商全称:ICS 功能描述:DDR Phase Lock Loop Zero Delay Clock Buffer |
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