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参数资料
| 型号： | ICS9342YF-PPP-T |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 146.62 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | 0.300 INCH, SSOP-48 |
| 文件页数： | 7/10页 |
| 文件大小： | 175K |
| 代理商： | ICS9342YF-PPP-T |
6
ICS9342
Third party brands and names are the property of their respective owners.
Electrical Characteristics - REF, OUT , OUT /2
TA = 0 - 70 C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated)
SYM BOL
CONDITIONS
M IN
TYP
M A X
UNITS
RDSP 5
1
VO = VDD*(0.5)
20
34
60
RDSN5
1
VO = VDD*(0.5)
20
31
60
VOH5
IOH = -12 mA
2.4
2.9
V
VOL5
IOL = 10 mA
0.33
0.4
V
IOH5
VOH = 2.0 V
-30
-20
mA
IOL5
VOL = 0.8 V
16
23
mA
Ris e Time
1
tr5
VOL = 0.4 V, VOH = 2.4 V; OUT
1.5
1.8
4
ns
Fall Time
1
tf5
VOH = 2.4 V, VOL = 0.4 V; OUT
1.5
2
4
ns
Duty Cycle
1
dt5
VT = 1.5 V; OUT
45
52
55
%
Ris e Time
1
tr5
VOL = 0.4 V, VOH = 2.4 V; OUT/2
1.5
2.2
4
ns
Fall Time
1
tf5
VOH = 2.4 V, VOL = 0.4 V; OUT/2
1.5
2.1
4
ns
Duty Cycle
1
dt5
VT = 1.5 V; OUT/2
45
50
55
%
Ris e Time
1
tr5
VOL = 0.4 V, VOH = 2.4 V; REF
1.5
2.7
4
ns
Fall Time
1
tf5
VOH = 2.4 V, VOL = 0.4 V; REF
1.5
2.8
4
ns
Duty Cycle
1
dt5
VT = 1.5 V; REF
45
50
55
%
tjcyc-cyc5
VT = 1.5 V; OUT, OUT/2
280
500
ps
tjcyc-cyc5
VT = 1.5 V; REF
450
1000
ps
1
Guaranteed b y des ign, no t 100% tes ted in production.
Jitter, Cycle-to-cycle1
Jitter, Cycle-to-cycle
1
PA RA M ETER
Output Lo w Voltage
Output High Current
Output High Voltage
Output Impedance
REF
OUT
OUT/2
Output Low Current
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS9342YF-T | 制造商:ICS 制造商全称:ICS 功能描述:133MHz Clock Generator and Integrated Buffer for PowerPC⑩ |
| ICS93701 | 制造商:ICS 制造商全称:ICS 功能描述:DDR Phase Lock Loop Clock Driver |
| ICS93701YGT | 制造商:ICS 制造商全称:ICS 功能描述:DDR Phase Lock Loop Clock Driver |
| ICS93705 | 制造商:ICS 制造商全称:ICS 功能描述:DDR Phase Lock Loop Zero Delay Clock Buffer |
| ICS93705YF-T | 制造商:ICS 制造商全称:ICS 功能描述:DDR Phase Lock Loop Zero Delay Clock Buffer |
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