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参数资料
| 型号： | ICS9342YF-PPP-T |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 146.62 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | 0.300 INCH, SSOP-48 |
| 文件页数： | 9/10页 |
| 文件大小： | 175K |
| 代理商： | ICS9342YF-PPP-T |
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ICS9342
Third party brands and names are the property of their respective owners.
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Power Management
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is
an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the
clock synthesizer.
Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to
a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The power
down latency should be as short as possible but conforming to the sequence requirements shown below. The REF and OUT
clocks are expected to be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping and
holding the REF clock outputs in the LOW state may require more than one clock cycle to complete.
Notes:
1. All timing is referenced to the Internal CPU (defined as inside the ICS9342 device).
2. As shown, the outputs Stop Low on the next falling edge after PD# goes low.
3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part.
4. The shaded sections on the VCO and the Crystal signals indicate an active clock.
5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
CPU
PCIREF
VCO
Crystal
PD#
相关PDF资料 |
PDF描述 |
|---|---|
| ICS93712YF-T | LOW SKEW CLOCK DRIVER, 6 TRUE OUTPUT(S), 6 INVERTED OUTPUT(S), PDSO28 |
| ICS93776YF-T | 93776 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| ICS93776YFLF-T | 93776 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| ICS95V157YGLF | PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| ICS95V157YGLF | PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS9342YF-T | 制造商:ICS 制造商全称:ICS 功能描述:133MHz Clock Generator and Integrated Buffer for PowerPC⑩ |
| ICS93701 | 制造商:ICS 制造商全称:ICS 功能描述:DDR Phase Lock Loop Clock Driver |
| ICS93701YGT | 制造商:ICS 制造商全称:ICS 功能描述:DDR Phase Lock Loop Clock Driver |
| ICS93705 | 制造商:ICS 制造商全称:ICS 功能描述:DDR Phase Lock Loop Zero Delay Clock Buffer |
| ICS93705YF-T | 制造商:ICS 制造商全称:ICS 功能描述:DDR Phase Lock Loop Zero Delay Clock Buffer |
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