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参数资料
| 型号： | IDT5V49EE702NDGI |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 2/34页 |
| 文件大小： | 0K |
| 描述： | IC PLL CLK GEN 200MHZ 28VQFN |
| 产品培训模块： | VersaClock™ III Programmable Clocks |
| 特色产品： | VersaClock III Timing Devices |
| 标准包装： | 75 |
| 系列： | VersaClock™ III |
| 类型： | 时钟发生器，多路复用器 |
| PLL： | 带旁路 |
| 输入： | LVCMOS，LVTTL，晶体 |
| 输出： | HCSL，LVCMOS，LVDS，LVPECL，LVTTL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:7 |
| 差分 - 输入:输出： | 无/是 |
| 频率 - 最大： | 500MHz |
| 除法器/乘法器： | 是/是 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-VFQFN 裸露焊盘 |
| 供应商设备封装： | 28-VFQFPN（4x4） |
| 包装： | 管件 |
| 其它名称： | 800-1918 IDT5V49EE702DLGI |
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IDT5V49EE702
EEPROM PROGRAMMABLE CLOCK GENERATOR
CLOCK SYNTHESIZER
IDT EEPROM PROGRAMMABLE CLOCK GENERATOR
10
IDT5V49EE702
REV M 092412
Spread Spectrum Generation (PLL3)
PLL3 support spread spectrum generation capability, which
users have the option of turning on and off. Spread
spectrum profile, frequency, and spread are fully
programmable (within limits). The technique is different from
that used in PLL0. The programmable spread spectrum
generation parameters are SS_D3[7:0], SSVCO[15:0],
SSENB, IP3[4:0] and RZ3[3:0] bits. These bits are in the
memory address range of 0x4C to 0x85 for PLL3. The
spread spectrum generation on PLL3 can be
enabled/disabled using the SSENB bit. To enable spread
spectrum, set SSENB = '1'.
For Spread Enabled:
Spread spectrum is configured using SS_D3(spread
spectrum reference divide)
and SSVCO (spread spectrum loop feedback counter).
SS is the total Spread Spectrum amount (I.e. center spread
+0.5% has a total spread of 1.0% and down spread -0.5%
has a total spread of 0.5%.)
Loop Filter
The loop filter for each PLL can be programmed to optimize
the jitter performance. The low-pass frequency response of
the PLL is the mechanism that dictates the jitter transfer
characteristics. The loop bandwidth can be extracted from
the jitter transfer. A narrow loop bandwidth is good for jitter
attenuation while a wide loop bandwidth is best for low-jitter
frequency generation. The specific loop filter components
that can be programmed are the resistor via the RZ[3:0] bits,
zero capacitor via the CZ bit (for PLL0, PLL1 and PLL2), and
the charge pump current via the IP[2:0] bits (for PLL0, PLL1
and PLL2) or IP[3:0] (for PLL3).
The following equations govern how the loop filter is set for
PLL0 - PLL2:
Resistor (Rz) = (RZ[0] + 2* RZ[1]+4* RZ[2] + 8* RZ[3])* 4.0
kOhm
Zero capacitor (Cz) = 196 pF + CZ* 217 pF
Pole capacitor (Cp) = 15 pF
Charge pump (Ip) = 6 * (IP[0] + 2*IP[1]+4*IP[2]) uA
VCO gain (KVCO) = 900 MHz/V * 2
π
The following equations govern how the loop filter is set for
PLL3:
For Non-Spread Spectrum Operation:
For Spread Spectrum Operation:
Zero capacitor (Cz) = 250 pF
Pole capacitor (Cp) = 15 pF
For Non-Spread Spectrum Operation:
For Spread Spectrum Operation:
VCO gain (KVCO) = 900 MHz/V * 2
π
=
SS_D3
(Eq. 10)
F
IN
4 * F
MOD
SSVCO =
F
VCO
F
MOD
[0.5 *
*
(Eq. 11)
( 1 + SS/400) + 5]
Resistor(Rz)=
(12.5 + 12.5*(RZ[1] + 2*RZ[2] + 4*RZ[3]))
* RZ[0] + 6*(1 – RZ[0])
kOhms (Eq. 12)
Resistor(Rz)=
(62.5 + 12.5*(RZ[1] + 2*RZ[2] + 4*RZ[3]))
* RZ[0] + 6*(1 – RZ[0])
kOhms (Eq. 13)
Charge
pump(Ip)
=
24* (1+(2* IP[0]) +(4* IP[1]) +(8* IP[2]))
A (Eq. 14)
3+(5* IP[3]) +(11* IP[4])
Charge
pump(Ip)
=
12* (1+(2* IP[0]) +(4* IP[1]) +(8* IP[2]))
A (Eq. 14)
27+(5* IP[3]) +(11* IP[4])
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT5V49EE702NDGI8 | 功能描述:IC PLL CLK GEN 200MHZ 28VQFN RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:VersaClock™ III 标准包装:1,000 系列:- 类型:时钟/频率合成器，扇出分配 PLL:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 除法器/乘法器:- 电源电压:- 工作温度:- 安装类型:表面贴装 封装/外壳:56-VFQFN 裸露焊盘 供应商设备封装:56-VFQFP-EP（8x8） 包装:带卷 (TR) 其它名称:844S012AKI-01LFT |
| IDT5V49EE703NDGI | 制造商:Integrated Device Technology Inc 功能描述:IC CLOCK GENERATOR |
| IDT5V49EE703NDGI8 | 制造商:Integrated Device Technology Inc 功能描述:IC CLK GEN EEPROM PROGR 28QFN |
| IDT5V49EE704NDGI | 功能描述:IC PLL CLK GEN 200MHZ 28VFQFPN RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:VersaClock™ III 标准包装:2,000 系列:- 类型:PLL 频率合成器 PLL:是 输入:晶体 输出:时钟 电路数:1 比率 - 输入:输出:1:1 差分 - 输入:输出:无/无 频率 - 最大:1GHz 除法器/乘法器:是/无 电源电压:4.5 V ~ 5.5 V 工作温度:-20°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-LSSOP（0.175"，4.40mm 宽） 供应商设备封装:16-SSOP 包装:带卷 (TR) 其它名称:NJW1504V-TE1-NDNJW1504V-TE1TR |
| IDT5V49EE704NDGI8 | 功能描述:IC PLL CLK GEN 200MHZ 28VFQFPN RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:VersaClock™ III 标准包装:1,000 系列:- 类型:时钟/频率合成器，扇出分配 PLL:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 除法器/乘法器:- 电源电压:- 工作温度:- 安装类型:表面贴装 封装/外壳:56-VFQFN 裸露焊盘 供应商设备封装:56-VFQFP-EP（8x8） 包装:带卷 (TR) 其它名称:844S012AKI-01LFT |
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