参数资料
型号: IDT70125L25JG
厂商: IDT, Integrated Device Technology Inc
文件页数: 10/15页
文件大小: 0K
描述: IC SRAM 18KBIT 25NS 52PLCC
标准包装: 24
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 18K(2K x 9)
速度: 25ns
接口: 并联
电源电压: 4.5 V ~ 5.5 V
工作温度: 0°C ~ 70°C
封装/外壳: 52-LCC(J 形引线)
供应商设备封装: 52-PLCC(19x19)
包装: 管件
IDT70121/IDT70125
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature
and Supply Voltage Range (6)
70121X25
70125X25
Com'l Only
70121X35
70125X35
Com'l
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
BUSY TIMING (For MASTER IDT70121)
BUSY Disable to Valid Data
Write Hold After BUSY
t BAA
t BDA
t BAC
t BDC
t WDD
t DDD
t APS
t BDD
t WH
BUSY Access Time from Address
BUSY Disable Time from Address
BUSY Access Time from Chip Enable
BUSY Disable Time from Chip Enable
(1)
Write Pulse to Data Delay
(1)
Write Data Valid to Read Data Delay
Arbitration Priority Set-up Time (2)
(3)
(5)
____
____
____
____
5
____
15
20
20
20
20
50
35
____
30
____
____
____
____
____
5
____
20
20
20
20
20
60
45
____
30
____
ns
ns
ns
ns
ns
ns
ns
BUSY INPUT TIMING (For SLAVE IDT70125)
t WB
t WH
Write to BUSY Input (4)
Write Hold After BUSY (5)
0
15
____
____
0
20
____
____
ns
ns
t WDD
Write Pulse to Data Delay
(1)
____
50
____
60
ns
t DDD
Write Data Valid to Read Data Delay
(1)
____
35
____
45
ns
2654 tbl 11a
70121X45
70125X45
Com'l Only
70121X55
70125X55
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
BUSY TIMING (For MASTER IDT 70121)
t BAA
t BDA
t BAC
t BDC
t WDD
t DDD
BUSY Access Time from Address
BUSY Disable Time from Address
BUSY Access Time from Chip Enable
BUSY Disable Time from Chip Enable
(1)
Write Pulse to Data Delay
(1)
Write Data Valid to Read Data Delay
____
____
____
____
20
20
20
20
70
55
____
____
____
____
30
30
30
30
80
65
ns
ns
ns
ns
BUSY Disable to Valid Data
t APS
t BDD
t WH
Arbitration Priority Set-up Time
(3)
Write Hold After BUSY (5)
(2)
5
____
20
____
35
____
5
____
20
____
45
____
ns
ns
ns
BUSY INPUT TIMING (For SLAVE IDT 70125)
t WB
t WH
Write to BUSY Input (4)
Write Hold After BUSY (5)
0
20
____
____
0
20
____
____
ns
ns
t WDD
Write Pulse to Data Delay
(1)
____
70
____
80
ns
t DDD
Write Data Valid to Read Data Delay
(1)
____
55
____
65
ns
NOTES :
1. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Write with Port-to-Port Read and BUSY .
2. To ensure that the earlier of the two ports wins.
3. t BDD is a calculated parameter and is the greater of 0, t WDD – t WP (actual) or t DDD – t DW (actual).
4. To ensure that a write cycle is inhibited on port 'B' during contention on port 'A'..
5. To ensure that a write cycle is completed on port 'B' after contention on port 'A'.
6. 'X' in part numbers indicates power rating (S or L).
10
6.42
2654 tbl 11b
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