参数资料
型号: IDT70125L25JG
厂商: IDT, Integrated Device Technology Inc
文件页数: 11/15页
文件大小: 0K
描述: IC SRAM 18KBIT 25NS 52PLCC
标准包装: 24
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 18K(2K x 9)
速度: 25ns
接口: 并联
电源电压: 4.5 V ~ 5.5 V
工作温度: 0°C ~ 70°C
封装/外壳: 52-LCC(J 形引线)
供应商设备封装: 52-PLCC(19x19)
包装: 管件
IDT70121/IDT70125
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Port-to-Port Read and BUSY (1,2,3)
t WC
ADDR 'A'
MATCH
t WP
R/ W 'A'
t DW
t DH
DATA IN'A'
ADDR 'B'
t APS (1)
VALID
MATCH
t DDD
BUSY 'B'
DATA OUT 'B'
t WDD
(4)
t BDA
t BDD
VALID
2654 drw 09
NOTES:
1. To ensure that the earlier of the two ports wins. t APS is ignored for Slave (IDT70125).
2. CE L = CE R = V IL
3. OE = V IL for the reading port.
4. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port "B" is oppsite from port "A".
Timing Waveform of Write with BUSY (3)
t WP
R/ W "A"
t WB
BUSY "B"
R/ W "B"
(2)
t WH
(1)
,
2654 drw 10
NOTES:
1. t WH must be met for both BUSY input (slave) and output (master).
2. BUSY is asserted on port 'B' blocking R/ W 'B', until BUSY 'B' goes HIGH.
3. All timing is the same for left and right ports. Port"A" may be either left or right port. Port "B" is the opposite from port "A".
Timing Waveform of BUSY Arbritration Controlled by CE Timing (1)
ADDR "A and B"
(1)
ADDRESSES MATCH
CE "A"
t APS (2)
CE "B"
t BAC
t BDC
BUSY "B"
2654 drw 11
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. If t APS is not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted
(70121 only).
11
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