参数资料
型号: IDT70125L25JG
厂商: IDT, Integrated Device Technology Inc
文件页数: 13/15页
文件大小: 0K
描述: IC SRAM 18KBIT 25NS 52PLCC
标准包装: 24
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 18K(2K x 9)
速度: 25ns
接口: 并联
电源电压: 4.5 V ~ 5.5 V
工作温度: 0°C ~ 70°C
封装/外壳: 52-LCC(J 形引线)
供应商设备封装: 52-PLCC(19x19)
包装: 管件
IDT70121/IDT70125
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt
Timing Waveform of Interrupt Mode (1)
t WC
Industrial and Commercial Temperature Ranges
ADDR 'A'
INTERRUPT SET ADDRESS (2)
R/ W 'A'
INT 'B'
NOTES: .
t AS (3)
t INS (3)
t WR (4)
2654 drw 13
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. See Interupt Truth Table.
3. Timing depends on which enable signal ( CE or R/ W ) is asserted last.
4. Timing depends on which enable signal ( CE or R/ W ) is de-asserted first.
Truth Tables
Truth Table I. Non-Contention Read/Write Control (4)
Left or Right Port (1)
R/ W
X
X
L
H
H
CE
H
H
L
L
L
OE
X
X
X
L
H
D 0-8
Z
Z
DATA IN
DATA OUT
Z
Function
Port Disab le and in Power-Down Mode, I SB2 or I SB4
CE R = CE L = H, Power-DownMode, I SB1 or I SB3
Data on Port Written Into Memory (2)
Data in Memory Output on Port (3)
High-Impedance Outputs
2654 tbl 13
NOTES:
1. A 0L – A 10L ≠ A 0R – A 10R .
2. If BUSY = L, data is not written.
3. If BUSY = L, data may not be valid, see t WDD and t DDD timing.
4. 'H' = V IH , 'L' = V IL , 'X' = DON’T CARE, 'Z' = HIGH IMPEDANCE
Truth Table II. Interrupt Flag (1,4)
Left Port
Right Port
R/ W L
L
X
X
X
CE L
L
X
X
L
OE L
X
X
X
L
A 10L -A 0L
7FF
X
X
7FE
INT L
X
X
L (3)
H (2)
R/ W R
X
X
L
X
CE R
X
L
L
X
OE R
X
L
X
X
A 10R -A 0R
X
7FF
7FE
X
INT R
L (2)
H (3)
X
X
Function
Set Right INT R Flag
Reset Right INT R Flag
Set Left INT L Flag
Reset Left INT L Flag
NOTES :
1. Assumes BUSY L = BUSY R = V IH
2. If BUSY L = V IL , then No Change.
3. If BUSY R = V IL , then No Change.
4. 'H' = HIGH,' L' = LOW,' X' = DON’T CARE
13
2654 tbl 14
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