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参数资料
| 型号： | IDT70125L25JG |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 8/15页 |
| 文件大小： | 0K |
| 描述： | IC SRAM 18KBIT 25NS 52PLCC |
| 标准包装： | 24 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 双端口，异步 |
| 存储容量： | 18K（2K x 9） |
| 速度： | 25ns |
| 接口： | 并联 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 52-LCC（J 形引线） |
| 供应商设备封装： | 52-PLCC（19x19） |
| 包装： | 管件 |
IDT70121/IDT70125
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range (4)
70121X25
70125X25
Com'l Only
70121X35
70125X35
Com'l
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
t WC
t EW
t AW
t AS
t WP
t WR
t DW
Write Cycle Time (4)
Chip Enable to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
Write Pulse Width (6)
Write Recovery Time
Data Valid to End-of-Write
25
20
20
0
20
0
12
____
____
____
____
____
____
____
35
30
30
0
30
0
20
____
____
____
____
____
____
____
ns
ns
ns
ns
ns
ns
ns
t HZ
Output High-Z Time
(1,2,3)
____
10
____
15
ns
t DH
Data Hold Time
(5)
0
____
0
____
ns
Write Enable to Output in High-Z
t WZ
(1,3)
____
10
____
15
ns
t OW
Output Active from End-of-Write
(1,2,3,5)
0
____
0
____
ns
2654 tbl 10a
70121X45
70125X45
Com'l Only
70121X55
70125X55
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
Write Pulse Width
t WC
t EW
t AW
t AS
t WP
t WR
t DW
Write Cycle Time (4)
Chip Enable to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
(6)
Write Recovery Time
Data Valid to End-of-Write
45
35
35
0
35
0
20
____
____
____
____
____
____
____
55
40
40
0
40
0
20
____
____
____
____
____
____
____
ns
ns
ns
ns
ns
ns
ns
t HZ
Output High-Z Time
(1,2,3)
____
20
____
30
ns
t DH
Data Hold Time
(5)
0
____
0
____
ns
t WZ
t OW
Write Enable to Output in High-Z (1,3)
Output Active from End-of-Write (1,2,3,5)
____
0
20
____
____
0
30
____
ns
ns
NOTES:
2654 tbl 10b
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter guaranteed by device characterization, but is not production tested.
3. For MASTER/SLAVE combination, t WC = t BAA + t WP, since R/W = V IL must occur after t BAA .
4. 'X' in part numbers indicates power rating (S or L).
5. The specified t DH must be met by the device supplying write date to the RAM under all operating conditions.
Although t DH and t OW values will vary over voltage and temperature. The actual t DH will always be smaller than the actual t OW.
6. If OE is LOW during a R/ W controlled write cycle, the write pulse width must be the larger of t WP or (t WZ + t DW ) to allow the I/O drivers to turn off data to be
placed on the bus for the required t DW . If OE is HIGH during a R/ W controlled write cycle, this requirement does not apply and the write pulse can be as short
as the specified t WP .
8
6.42
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT70125L25JG8 | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 18KBIT 25NS 52PLCC |
| IDT70125L25JGI | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT |
| IDT70125L25L52 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x9 Dual-Port SRAM |
| IDT70125L35J | 功能描述:IC SRAM 18KBIT 35NS 52PLCC RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:72 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 同步 存储容量:9M（256K x 36） 速度:75ns 接口:并联 电源电压:3.135 V ~ 3.465 V 工作温度:-40°C ~ 85°C 封装/外壳:100-LQFP 供应商设备封装:100-TQFP（14x14） 包装:托盘 其它名称:71V67703S75PFGI |
| IDT70125L35J8 | 功能描述:IC SRAM 18KBIT 35NS 52PLCC RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:72 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 同步 存储容量:9M（256K x 36） 速度:75ns 接口:并联 电源电压:3.135 V ~ 3.465 V 工作温度:-40°C ~ 85°C 封装/外壳:100-LQFP 供应商设备封装:100-TQFP（14x14） 包装:托盘 其它名称:71V67703S75PFGI |
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