参数资料
型号: IDT70125L25JG
厂商: IDT, Integrated Device Technology Inc
文件页数: 12/15页
文件大小: 0K
描述: IC SRAM 18KBIT 25NS 52PLCC
标准包装: 24
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 18K(2K x 9)
速度: 25ns
接口: 并联
电源电压: 4.5 V ~ 5.5 V
工作温度: 0°C ~ 70°C
封装/外壳: 52-LCC(J 形引线)
供应商设备封装: 52-PLCC(19x19)
包装: 管件
IDT70121/IDT70125
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt
Industrial and Commercial Temperature Ranges
Timing Waveform of BUSY Arbritration Controlled by Address (1)
t RC OR t WC
ADDR 'A'
ADDR 'B'
BUSY 'B'
NOTES:
t APS (2)
ADDRESSES MATCH
t BAA
ADDRESSES DO NOT MATCH
t BDA
2654 drw 12
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. If t APS is not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted
(70121 only).
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range (1)
70121X25
70125X25
Com'l Only
70121X35
70125X35
Com'l
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
t AS
t WR
t INS
t INR
Address Set-up Time
Write Recovery Time
Interrupt Set Time
Interrupt Reset Time
0
0
____
____
____
____
25
25
0
0
____
____
____
____
35
35
ns
ns
ns
ns
2654 tbl 12a
70121X45
70125X45
Com'l Only
70121X55
70125X55
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
t AS
t WR
t INS
t INR
Address Set-up Time
Write Recovery Time
Interrupt Set Time
Interrupt Reset Time
0
0
____
____
____
____
40
40
0
0
____
____
____
____
45
45
ns
ns
ns
ns
2654 tbl 12b
NOTES :
1. 'X' in part numbers indicates power rating (S or L).
12
6.42
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