- 您现在的位置：买卖IC网 > Datasheet目录328 > IDT70125L25JG (IDT, Integrated Device Technology Inc)IC SRAM 18KBIT 25NS 52PLCC Datasheet资料下载
参数资料
| 型号： | IDT70125L25JG |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 9/15页 |
| 文件大小： | 0K |
| 描述： | IC SRAM 18KBIT 25NS 52PLCC |
| 标准包装： | 24 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 双端口，异步 |
| 存储容量： | 18K（2K x 9） |
| 速度： | 25ns |
| 接口： | 并联 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 52-LCC（J 形引线） |
| 供应商设备封装： | 52-PLCC（19x19） |
| 包装： | 管件 |
IDT70121/IDT70125
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt
Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, R/ W Controlled Timing (1,5,8)
t WC
ADDRESS
t HZ (7)
OE
CE
t AW
t WR (3)
R/ W
t AS (6)
t WP (2)
t HZ
(7)
t WZ (7)
t OW
DATA OUT
(4)
t DW
t DH
(4)
DATA IN
2654 drw 07
Timing Waveform of Write Cycle No. 2, CE Controlled Timing (1,5)
t WC
ADDRESS
t AW
CE
t AS (6)
t EW (2)
t WR
(3)
R/ W
t DW
t DH
DATA IN
2654 drw 08
NOTES:
1. R/ W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (t EW or t WP ) of a CE = V IL and a R/ W = V IL
3. t WR is measured from the earlier of CE or R/ W going HIGH to the end of the write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE LOW transition occurs simultaneously with or after the R/ W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal ( CE or R/ W ) is asserted last.
7. This parameter is determined be device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
(Figure 2).
8. If OE is LOW during a R/ W controlled write cycle, the write pulse width must be the larger of t WP or (t WZ + t DW ) to allow the I/O drivers to turn off data to be
placed on the bus for the required t DW . If OE is HIGH during a R/ W controlled write cycle, this requirement does not apply and the write pulse can be as short
as the specified t WP .
9
相关PDF资料 |
PDF描述 |
|---|---|
| IDT7014S12JG | IC SRAM 36KBIT 12NS 52PLCC |
| IDT7015L35G | IC SRAM 72KBIT 35NS 68PGA |
| IDT7016L35G | IC SRAM 144KBIT 35NS 68PGA |
| IDT7019L20PFI | IC SRAM 1.125MBIT 20NS 100TQFP |
| IDT7024L55G | IC SRAM 64KBIT 55NS 84PGA |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT70125L25JG8 | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 18KBIT 25NS 52PLCC |
| IDT70125L25JGI | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT |
| IDT70125L25L52 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x9 Dual-Port SRAM |
| IDT70125L35J | 功能描述:IC SRAM 18KBIT 35NS 52PLCC RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:72 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 同步 存储容量:9M（256K x 36） 速度:75ns 接口:并联 电源电压:3.135 V ~ 3.465 V 工作温度:-40°C ~ 85°C 封装/外壳:100-LQFP 供应商设备封装:100-TQFP（14x14） 包装:托盘 其它名称:71V67703S75PFGI |
| IDT70125L35J8 | 功能描述:IC SRAM 18KBIT 35NS 52PLCC RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:72 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 同步 存储容量:9M（256K x 36） 速度:75ns 接口:并联 电源电压:3.135 V ~ 3.465 V 工作温度:-40°C ~ 85°C 封装/外壳:100-LQFP 供应商设备封装:100-TQFP（14x14） 包装:托盘 其它名称:71V67703S75PFGI |
发布紧急采购，3分钟左右您将得到回复。