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参数资料
| 型号： | IDT72V2113L10PFI8 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 39/46页 |
| 文件大小： | 0K |
| 描述： | IC FIFO SUPERSYNCII 10NS 80-TQFP |
| 标准包装： | 750 |
| 系列： | 72V |
| 功能： | 同步 |
| 存储容量： | 4.7Mb（262k x 18） |
| 访问时间： | 10ns |
| 电源电压： | 3.15 V ~ 3.45 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 80-LQFP |
| 供应商设备封装： | 80-TQFP（14x14） |
| 包装： | 带卷 (TR) |
| 其它名称： | 72V2113L10PFI8 |
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IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
JUNE 1, 2010
IDT72V2103/72V2113 JTAG Device Identification Register
31(MSB)
28 27
12 11
1 0(LSB)
Version (4 bits)
Part Number (16-bit) Manufacturer ID (11-bit)
0X0
0X33
1
Device
Part# Field
IDT72V2103
042E
IDT72V2113
042F
THE INSTRUCTION REGISTER
TheInstructionregisterallowsaninstructiontobeshiftedinseriallyintothe
processor at the rising edge of TCLK.
The Instruction is used to select the test to be performed, or the test data
registertobeaccessed,orboth. Theinstructionshiftedintotheregisterislatched
at the completion of the shifting process when the TAP controller is at Update-
IRstate.
The instruction register must contain 4 bit instruction register-based cells
whichcanholdinstructiondata. Thesemandatorycellsarelocatednearestthe
serial outputs they are the least significant bits.
TEST DATA REGISTER
The Test Data register contains three test data registers: the Bypass, the
Boundary Scan register and Device ID register.
These registers are connected in parallel between a common serial input
and a common serial data output.
The following sections provide a brief description of each element. For a
completedescription,refertotheIEEEStandardTestAccessPortSpecification
(IEEE Std. 1149.1-1990).
TEST BYPASS REGISTER
The register is used to allow test data to flow through the device from TDI
toTDO. Itcontainsasinglestageshiftregisterforaminimumlengthinserialpath.
When the bypass register is selected by an instruction, the shift register stage
is set to a logic zero on the rising edge of TCLK when the TAP controller is in
the Capture-DR state.
The operation of the bypass register should not have any effect on the
operation of the device in response to the BYPASS instruction.
THE BOUNDARY-SCAN REGISTER
The Boundary Scan Register allows serial data TDI be loaded in to or read
out of the processor input/output ports. The Boundary Scan Register is a part
of the IEEE 1149.1-1990 Standard JTAG Implementation.
THE DEVICE IDENTIFICATION REGISTER
The Device Identification Register is a Read Only 32-bit register used to
specify the manufacturer, part number and version of the processor to be
determined through the TAP in response to the IDCODE instruction.
IDT JEDEC ID number is 0xB3. This translates to 0x33 when the parity
is dropped in the 11-bit Manufacturer ID field.
FortheIDT72V2103/72V2113,thePartNumberfieldcontainsthefollowing
values:
JTAG INSTRUCTION REGISTER
TheInstructionregisterallowsinstructiontobeseriallyinputintothedevice
when the TAP controller is in the Shift-IR state. The instruction is decoded to
perform the following:
Select test data registers that may operate while the instruction is
current. The other test data registers should not interfere with chip
operation and the selected data register.
Definetheserialtestdataregisterpaththatisusedtoshiftdatabetween
TDI and TDO during data register scanning.
The Instruction Register is a 4 bit field (i.e. IR3, IR2, IR1, IR0) to decode
16 different possible instructions. Instructions are decoded as follows.
Hex
Instruction
Function
Value
0x00
EXTEST
Select Boundary Scan Register
0x02
IDCODE
Select Chip Identification data register
0x01
SAMPLE/PRELOAD
Select Boundary Scan Register
0x03
HIGH-IMPEDANCE
JTAG
0x0F
BYPASS
Select Bypass Register
Table 6. JTAG Instruction Register Decoding
The following sections provide a brief description of each instruction. For
acompletedescriptionrefertotheIEEEStandardTestAccessPortSpecification
(IEEE Std. 1149.1-1990).
EXTEST
The required EXTEST instruction places the IC into an external boundary-
testmodeandselectstheboundary-scanregistertobeconnectedbetweenTDI
and TDO. During this instruction, the boundary-scan register is accessed to
drive test data off-chip via the boundary outputs and receive test data off-chip
via the boundary inputs. As such, the EXTEST instruction is the workhorse of
IEEE. Std 1149.1, providing for probe-less testing of solder-joint opens/shorts
and of logic cluster function.
IDCODE
TheoptionalIDCODEinstructionallowstheICtoremaininitsfunctionalmode
andselectstheoptionaldeviceidentificationregistertobeconnectedbetween
TDIandTDO.Thedeviceidentificationregisterisa32-bitshiftregistercontaining
information regarding the IC manufacturer, device type, and version code.
Accessingthedeviceidentificationregisterdoesnotinterferewiththeoperation
oftheIC.Also,accesstothedeviceidentificationregistershouldbeimmediately
available, via a TAP data-scan operation, after power-up of the IC or after the
TAP has been reset using the optional
TRSTpinorbyotherwisemovingtothe
Test-Logic-Resetstate.
SAMPLE/PRELOAD
The required SAMPLE/PRELOAD instruction allows the IC to remain in a
normalfunctionalmodeandselectstheboundary-scanregistertobeconnected
between TDI and TDO. During this instruction, the boundary-scan register can
be accessed via a date scan operation, to take a sample of the functional data
enteringandleavingtheIC.Thisinstructionisalsousedtopreloadtestdatainto
the boundary-scan register before loading an EXTEST instruction.
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| IDT72V2113L15PF | 功能描述:IC FIFO SUPERSYNCII 15NS 80-TQFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT72V2113L15PF8 | 功能描述:IC FIFO SUPERSYNCII 15NS 80-TQFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT72V2113L6BC | 功能描述:IC FIFO SUPERSYNCII 6NS 100-BGA RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT72V2113L6PF | 功能描述:IC FIFO SUPERSYNCII 6NS 80-TQFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
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