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参数资料
| 型号： | IDT72V2113L10PFI8 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 9/46页 |
| 文件大小： | 0K |
| 描述： | IC FIFO SUPERSYNCII 10NS 80-TQFP |
| 标准包装： | 750 |
| 系列： | 72V |
| 功能： | 同步 |
| 存储容量： | 4.7Mb（262k x 18） |
| 访问时间： | 10ns |
| 电源电压： | 3.15 V ~ 3.45 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 80-LQFP |
| 供应商设备封装： | 80-TQFP（14x14） |
| 包装： | 带卷 (TR) |
| 其它名称： | 72V2113L10PFI8 |
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IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
JUNE 1, 2010
SERIAL PROGRAMMING MODE
If Serial Programming mode has been selected, as described above, then
programmingof
PAEandPAFvaluescanbeachievedbyusingacombination
ofthe
LD,SEN,WCLKandSIinputpins.ProgrammingPAEandPAFproceeds
as follows: when
LD and SEN are set LOW, data on the SI input are written,
onebitforeachWCLKrisingedge,startingwiththeEmptyOffsetLSBandending
with the Full Offset MSB. If x9 to x9 mode is selected, a total of 36 bits for the
IDT72V2103 and 38 bits for the IDT72V2113. For any other mode of operation
(thatincludesx18buswidthoneithertheInputorOutput),minus2bitsfromthe
values above. So, a total of 34 bits for the IDT72V2103 and 36 bits for the
IDT72V2113. See Figure 15, Serial Loading of Programmable Flag Regis-
ters, for the timing diagram for this mode.
Using the serial method, individual registers cannot be programmed
selectively.
PAE and PAF can show a valid status only after the complete set
of bits (for all offset registers) has been entered. The registers can be
reprogrammed as long as the complete set of new offset bits is entered. When
LD is LOW and SEN is HIGH, no serial write to the registers can occur.
Write operations to the FIFO are allowed before and during the serial
programmingsequence.Inthiscase,theprogrammingofalloffsetbitsdoesnot
have to occur at once. A select number of bits can be written to the SI input and
then, by bringing
LD and SEN HIGH, data can be written to FIFO memory via
Dn by toggling
WEN. When WEN is brought HIGH with LD and SEN restored
to a LOW, the next offset bit in sequence is written to the registers via SI. If an
interruptionofserialprogrammingisdesired,itissufficienteithertoset
LDLOW
and deactivate
SENortosetSENLOWanddeactivateLD.OnceLDandSEN
are both restored to a LOW level, serial offset programming continues.
From the time serial programming has begun, neither programmable flag
will be valid until the full set of bits required to fill all the offset registers has been
written.MeasuringfromtherisingWCLKedgethatachievestheabovecriteria;
PAFwillbevalidaftertwomorerisingWCLKedgesplustPAF,PAEwillbevalid
after the next two rising RCLK edges plus tPAE plus tSKEW2.
It is not possible to read the flag offset values in a serial mode.
PARALLEL PROGRAMMING MODE
IfParallelProgrammingmodehasbeenselected,asdescribedabove,then
programmingof
PAEandPAFvaluescanbeachievedbyusingacombination
of the
LD,WCLK,WENandDninputpins.IftheFIFOisconfiguredforaninput
bus width and output bus width both set to x9, then the total number of write
operations required to program the offset registers is 6 for the IDT72V2103/
72V2113. Refer to Figure 3, Programmable Flag Offset Programming
Sequence, for a detailed diagram of the data input lines D0-Dn used during
parallel programming. If the FIFO is configured for an input to output bus width
ofx9tox18,x18tox9orx18tox18,thenthefollowingnumberofwriteoperations
are required. For an input bus width of x18 total of 4 write operations will be
required for the IDT72V2103/72V2113. For an input bus width of x9 a total of
6 will be required for the IDT72V2103/72V2113. Refer to Figure 3, Program-
mable Flag Offset Programming Sequence, for a detailed diagram.
For example, programming
PAE and PAF on the IDT72V2103/72V2113
configured for x18 bus width proceeds as follows: when
LD and WEN are set
LOW,dataontheinputsDnarewrittenintotheLSBoftheEmptyOffsetRegister
onthefirstLOW-to-HIGHtransitionofWCLK.UponthesecondLOW-to-HIGH
transitionofWCLK,dataarewrittenintotheMSBoftheEmptyOffsetRegister.
On the third LOW-to-HIGH transition of WCLK, data are written into the LSB of
the Full Offset Register. On the fourth LOW-to-HIGH transition of WCLK, data
are written into the MSB of the Full Offset Register. The fifth LOW-to-HIGH
transition of WCLK, data are written, once again to the Empty Offset Register.
Note that for x9 bus width, one extra Write cycle is required for both the Empty
Offset Register and Full Offset Register. See Figure 16, Parallel Loading of
Programmable Flag Registers, for the timing diagram for this mode.
Theactofwritingoffsetsinparallelemploysadedicatedwriteoffsetregister
pointer. The act of reading offsets employs a dedicated read offset register
pointer. The two pointers operate independently; however, a read and a write
shouldnotbeperformedsimultaneouslytotheoffsetregisters.AMasterReset
initializes both pointers to the Empty Offset (LSB) register. A Partial Reset has
no effect on the position of these pointers. Refer to Figure 3, Programmable
Flag Offset Programming Sequence, for a detailed diagram of the data input
lines D0-Dn used during parallel programming.
Write operations to the FIFO are allowed before and during the parallel
programming sequence. In this case, the programming of all offset registers
does not have to occur at one time. One, two or more offset registers can be
written and then by bringing
LD HIGH, write operations can be redirected to
theFIFOmemory.When
LDissetLOWagain,andWENisLOW,thenextoffset
register in sequence is written to. As an alternative to holding
WENLOWand
toggling
LD,parallelprogrammingcanalsobeinterruptedbysettingLDLOW
and toggling
WEN.
Note that the status of a programmable flag (
PAEorPAF)outputisinvalid
during the programming process. From the time parallel programming has
begun, a programmable flag output will not be valid until the appropriate offset
word has been written to the register(s) pertaining to that flag. Measuring from
the rising WCLK edge that achieves the above criteria;
PAFwillbevalidafter
twomorerisingWCLKedgesplustPAF,
PAEwillbevalidafterthenexttworising
RCLK edges plus tPAE plus tSKEW2.
The act of reading the offset registers employs a dedicated read offset
register pointer. The contents of the offset registers can be read on the Q0-Qn
pins when
LDissetLOWandRENissetLOW.IftheFIFOisconfiguredforan
inputbuswidthandoutputbuswidthbothsettox9,thenthetotalnumberofread
operations required to read the offset registers is 6 for the IDT72V2103/
72V2113. Refer to Figure 3, Programmable Flag Offset Programming
Sequence, for a detailed diagram of the data input lines D0-Dn used during
parallel programming. If the FIFO is configured for an input to output bus width
of x9 to x18, x18 to x9 or x18 to x18, then the following number of read
operations are required: for an output bus width of x18 a total of 4 read
operations will be required for the IDT72V2103/72V2113. For an output bus
width of x9 a total of 6 will be required for the IDT72V2103/72V2113. Refer to
Figure 3, Programmable Flag Offset Programming Sequence, for a detailed
diagram. For example, reading
PAE andPAF on the IDT72V2103/72V2113
configured for x18 bus width proceeds as follows: data are read via Qn from
the Empty Offset Register on the first and second LOW-to-HIGH transition of
RCLK. Upon the third and fourth LOW-to-HIGH transition of RCLK, data are
read from the Full Offset Register. The fifth and sixth transition of RCLK reads,
once again, from the Empty Offset Register. Note that for a x9 bus width, one
extra Read cycle is required for both the Empty Offset Register and Full Offset
Register. See Figure 17, Parallel Read of Programmable Flag Registers, for
the timing diagram for this mode.
It is permissible to interrupt the offset register read sequence with reads or
writes to the FIFO. The interruption is accomplished by deasserting
REN,LD,
or both together. When
REN and LD are restored to a LOW level, reading of
theoffsetregisterscontinueswhereitleftoff.Itshouldbenoted,andcareshould
be taken from the fact that when a parallel read of the flag offsets is performed,
the data word that was present on the output lines Qn will be overwritten.
Parallel reading of the offset registers is always permitted regardless of
which timing mode (IDT Standard or FWFT modes) has been selected.
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| IDT72V2113L15PF | 功能描述:IC FIFO SUPERSYNCII 15NS 80-TQFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT72V2113L15PF8 | 功能描述:IC FIFO SUPERSYNCII 15NS 80-TQFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT72V2113L6BC | 功能描述:IC FIFO SUPERSYNCII 6NS 100-BGA RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT72V2113L6PF | 功能描述:IC FIFO SUPERSYNCII 6NS 80-TQFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT72V2113L6PF8 | 功能描述:IC FIFO SUPERSYNCII 6NS 80-TQFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
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