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| 型号： | IDT72V2113L10PFI8 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 4/46页 |
| 文件大小： | 0K |
| 描述： | IC FIFO SUPERSYNCII 10NS 80-TQFP |
| 标准包装： | 750 |
| 系列： | 72V |
| 功能： | 同步 |
| 存储容量： | 4.7Mb（262k x 18） |
| 访问时间： | 10ns |
| 电源电压： | 3.15 V ~ 3.45 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 80-LQFP |
| 供应商设备封装： | 80-TQFP（14x14） |
| 包装： | 带卷 (TR) |
| 其它名称： | 72V2113L10PFI8 |
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IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
JUNE 1, 2010
FUNCTIONAL DESCRIPTION
TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH
(FWFT) MODE
The IDT72V2103/72V2113 support two different timing modes of opera-
tion: IDT Standard mode or First Word Fall Through (FWFT) mode. The
selection of which mode will operate is determined during Master Reset, by
the state of the FWFT/SI input.
If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard mode
will be selected. This mode uses the Empty Flag (
EF) to indicate whether or
not there are any words present in the FIFO. It also uses the Full Flag function
(
FF) to indicate whether or not the FIFO has any free space for writing. In IDT
Standard mode, every word read from the FIFO, including the first, must be
requested using the Read Enable (
REN) and RCLK.
If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will be
selected. This mode uses Output Ready (
OR)toindicatewhetherornotthere
is valid data at the data outputs (Qn). It also uses Input Ready (
IR) to indicate
whether or not the FIFO has any free space for writing. In the FWFT mode,
thefirstwordwrittentoanemptyFIFOgoesdirectlytoQnafterthreeRCLKrising
edges,
REN = LOW is not necessary. Subsequent words must be accessed
using the Read Enable (
REN) and RCLK.
Varioussignals,bothinputandoutputsignalsoperatedifferentlydepending
on which timing mode is in effect.
IDT STANDARD MODE
In this mode, the status flags,
FF, PAF, HF, PAE, and EF operate in the
manner outlined in Table 3. To write data into to the FIFO, Write Enable (
WEN)
mustbeLOW.DatapresentedtotheDATAINlineswillbeclockedintotheFIFO
on subsequent transitions of the Write Clock (WCLK). After the first write is
performed, the Empty Flag (
EF)willgoHIGH.Subsequentwriteswillcontinue
to fill up the FIFO. The Programmable Almost-Empty flag (
PAE)willgoHIGH
after n + 1 words have been loaded into the FIFO, where n is the empty offset
value. The default setting for these values are stated in the footnote of Table 2.
Thisparameterisalsouserprogrammable.SeesectiononProgrammableFlag
OffsetLoading.
If one continued to write data into the FIFO, and we assumed no read
operationsweretakingplace,theHalf-Fullflag(
HF)wouldtoggletoLOWonce
(D/2 + 1) words were written into the FIFO. If x18 Input or x18 Output bus Width
is selected, (D/2 + 1) = the 65,537th word for the IDT72V2103 and 131,073rd
word for the IDT72V2113. If both x9 Input and x9 Output bus Widths are
selected, (D/2 + 1) = the 131,073rd word for the IDT72V2103 and 262,145th
word for the IDT72V2113. Continuing to write data into the FIFO will cause the
Programmable Almost-Full flag (
PAF) to go LOW. Again, if no reads are
performed, the
PAFwillgoLOWafter(D-m)writestotheFIFO.Ifx18Inputor
x18OutputbusWidthisselected,(D-m) = (131,072-m)writesfortheIDT72V2103
and(262,144-m)writesfortheIDT72V2113.Ifbothx9Inputandx9Outputbus
Widths are selected, (D-m) = (262,144-m) writes for the IDT72V2103 and
(524,288-m) writes for the IDT72V2113. The offset “m” is the full offset value.
The default setting for these values are stated in the footnote of Table 2. This
parameter is also user programmable. See section on Programmable Flag
OffsetLoading.
When the FIFO is full, the Full Flag (
FF)willgoLOW,inhibitingfurtherwrite
operations.Ifnoreadsareperformedafterareset,
FFwillgoLOWafterDwrites
to the FIFO. If the x18 Input or x18 Output bus Width is selected, D = 131,072
writes for the IDT72V2103 and 262,144 writes for the IDT72V2113. If both x9
Input and x9 Output bus Widths are selected, D = 262,144 writes for the
IDT72V2103 and 524,288 writes for the IDT72V2113, respectively.
If the FIFO is full, the first read operation will cause
FF to go HIGH.
Subsequentreadoperationswillcause
PAFandHFtogoHIGHattheconditions
described in Table 3. If further read operations occur, without write operations,
PAE will go LOW when there are n words in the FIFO, where n is the empty
offsetvalue.ContinuingreadoperationswillcausetheFIFOtobecomeempty.
When the last word has been read from the FIFO, the
EFwillgoLOWinhibiting
further read operations.
REN is ignored when the FIFO is empty.
When configured in IDT Standard mode, the
EFandFFoutputsaredouble
register-bufferedoutputs.
Relevant timing diagrams for IDT Standard mode can be found in Figure
7, 8 and 11.
FIRST WORD FALL THROUGH MODE (FWFT)
In this mode, the status flags,
IR, PAF, HF, PAE, and OR operate in the
manner outlined in Table 4. To write data into the FIFO,
WEN must be LOW.
DatapresentedtotheDATAINlineswillbeclockedintotheFIFOonsubsequent
transitions of WCLK. After the first write is performed, the Output Ready (
OR)
flag will go LOW. Subsequent writes will continue to fill up the FIFO.
PAEwillgo
HIGH after n+2 words have been loaded into the FIFO, where n is the empty
offsetvalue.ThedefaultsettingforthesevaluesarestatedinthefootnoteofTable
2. This parameter is also user programmable. See section on Programmable
Flag Offset Loading.
If one continued to write data into the FIFO, and we assumed no read
operations were taking place, the
HF would toggle to LOW once the (D/2 + 2)
wordswerewrittenintotheFIFO.Ifx18Inputorx18OutputbusWidthisselected,
(D/2 + 2) = the 65,538th word for the IDT72V2103 and 131,074th word for the
IDT72V2113. If both x9 Input and x9 Output bus Widths are selected,
(D/2 + 2) = the 131,074th word for the IDT72V2103 and 262,146th word for
the IDT72V2113. Continuing to write data into the FIFO will cause the
PAF to
goLOW.Again,ifnoreadsareperformed,the
PAFwillgoLOWafter(D-m)writes
totheFIFO.Ifx18Inputorx18OutputbusWidthisselected,(D-m) = (131,073-m)
writes for the IDT72V2103 and (262,145-m) writes for the IDT72V2113. If both
x9 Input and x9 Output bus Widths are selected, (D-m) = (262,145-m) writes
for the IDT72V2103 and (524,289-m) writes for the IDT72V2113. The offset
m is the full offset value. The default setting for these values are stated in the
footnote of Table 2.
WhentheFIFOisfull,theInputReady(
IR)flagwillgoHIGH,inhibitingfurther
write operations. If no reads are performed after a reset,
IR will go HIGH after
D writes to the FIFO. If x18 Input or x18 Output bus Width is selected,
D = 131,073writesfortheIDT72V2103and262,145writesfortheIDT72V2113.
If both x9 Input and x9 Output bus Widths are selected, D = 262,145 writes for
the IDT72V2103 and 524,289 writes for the IDT72V2113, respectively. Note
thattheadditionalwordinFWFTmodeisduetothecapacityofthememoryplus
outputregister.
If the FIFO is full, the first read operation will cause the
IR flag to go LOW.
Subsequent read operations will cause the
PAF and HF to go HIGH at the
conditions described in Table 4. If further read operations occur, without write
operations, the
PAEwillgoLOWwhentherearen+1wordsintheFIFO,where
n is the empty offset value. Continuing read operations will cause the FIFO to
become empty. When the last word has been read from the FIFO,
OR will go
HIGHinhibitingfurtherreadoperations.
RENisignoredwhentheFIFOisempty.
When configured in FWFT mode, the
OR flag output is triple register-
buffered, and the
IRflag output is double register-buffered.
Relevant timing diagrams for FWFT mode can be found in Figure 9, 10 and
12.
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| IDT72V2113L6PF | 功能描述:IC FIFO SUPERSYNCII 6NS 80-TQFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
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