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参数资料
| 型号： | IDT72V2113L10PFI8 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 43/46页 |
| 文件大小： | 0K |
| 描述： | IC FIFO SUPERSYNCII 10NS 80-TQFP |
| 标准包装： | 750 |
| 系列： | 72V |
| 功能： | 同步 |
| 存储容量： | 4.7Mb（262k x 18） |
| 访问时间： | 10ns |
| 电源电压： | 3.15 V ~ 3.45 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 80-LQFP |
| 供应商设备封装： | 80-TQFP（14x14） |
| 包装： | 带卷 (TR) |
| 其它名称： | 72V2113L10PFI8 |
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6
IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
JUNE 1, 2010
PIN DESCRIPTION (TQFP & BGA PACKAGES)
NOTE:
1. Inputs should not change state after Master Reset.
Symbol
Name
I/O
Description
BE(1)
*Big-Endian/
I
During Master Reset, a LOW on
BE will select Big-Endian operation. A HIGH on BE during Master Reset will
Little-Endian
selectLittle-Endianformat.
D0–D17
DataInputs
I
Data inputs for a 18- or 9-bit bus. When in 18-bit mode, D0–D17 are used. When in 9-bit mode, D0–D8 are used
and the unused inputs, D9–D17, should be tied LOW.
EF/OR
Empty Flag/
O
In the IDT Standard mode, the
EF function is selected. EF indicates whether or not the FIFO memory is empty.In
Output Ready
FWFT mode, the
OR function is selected. OR indicates whether or not there is valid data available at the outputs.
FF/IR
Full Flag/
O
In the IDT Standard mode, the
FF function is selected. FF indicates whether or not the FIFO memory is full. In the
Input Ready
FWFT mode, the
IR function is selected. IR indicates whether or not there is space available for writing to the FIFO
memory.
FSEL0(1) Flag Select Bit 0
I
During Master Reset, this input along with FSEL1 and the
LD pin, will select the default offset values for the
programmable flags
PAE and PAF. There are up to eight possible settings available.
FSEL1(1) Flag Select Bit 1
I
During Master Reset, this input along with FSEL0 and the
LD pin will select the default offset values for the
programmable flags
PAE and PAF. There are up to eight possible settings available.
FWFT/SI First Word Fall
I
During Master Reset, selects First Word Fall Through or IDT Standard mode. After Master Reset, this pin functions
Through/Serial In
as a serial input for loading offset registers.
HF
Half-Full Flag
O
HF indicates whether the FIFO memory is more or less than half-full.
IP(1)
Interspersed Parity
I
During Master Reset, a LOW on IP will select Non-Interspersed Parity mode. A HIGH will select Interspersed
Parity mode. Interspersed Parity control only has an effect during parallel programming of the offset registers. It
does not effect the data written to and read from the FIFO.
IW(1)
InputWidth
I
This pin selects the bus width of the write port. During Master Reset, when IW is LOW, the write port will be
configured with a x18 bus width. If IW is HIGH, the write port will be a x9 bus width.
LD
Load
I
This is a dual purpose pin. During Master Reset, the state of the
LD input,alongwithFSEL0andFSEL1,determines
one of eight default offset values for the
PAEandPAFflags,alongwiththemethodbywhichtheseoffsetregisterscan
be programmed, parallel or serial (see Table 2). After Master Reset, this pin enables writing to and reading from the
offsetregisters.
MRS
Master Reset
I
MRSinitializesthereadandwritepointerstozeroandsetstheoutputregistertoallzeroes.DuringMasterReset,the
FIFO is configured for either FWFT or IDT Standard mode, Bus-Matching configurations, one of eight programmable
flagdefaultsettings,serialorparallelprogrammingoftheoffsetsettings,Big-Endian/Little-Endianformat,zerolatency
timing mode, interspersed parity, and synchronous versus asynchronous programmable flag timing modes.
OE
OutputEnable
I
OE controls the output impedance of Qn.
OW(1)
OutputWidth
I
This pin selects the bus width of the read port. During Master Reset, when OW is LOW, the read port willbeconfig-
ured with a x18 bus width. If OW is HIGH, the read port will be a x9 bus width.
PAE
Programmable
O
PAE goes LOW if the number of words in the FIFO memory is less than offset n, which is stored in the Empty Offset
Almost-EmptyFlag
register.
PAE goes HIGH if the number of words in the FIFO memory is greater than or equal to offset n.
PAF
Programmable
O
PAF goes HIGH if the number of free locations in the FIFO memory is more than offset m, which is stored in the
Almost-FullFlag
Full Offset register.
PAF goes LOW if the number of free locations in the FIFO memory is less than or equal to m.
PFM(1)
Programmable
I
During Master Reset, a LOW on PFM will select Asynchronous Programmable flag timing mode. A HIGH on PFM
Flag Mode
will select Synchronous Programmable flag timing mode.
PRS
PartialReset
I
PRS initializes the read and write pointers to zero and sets the output register to all zeroes. During Partial Reset,
the existing mode (IDT or FWFT), programming method (serial or parallel), and programmable flag settings are
all retained.
Q0–Q17
DataOutputs
O
Data outputs for a 18- or 9-bit bus. When in 18-bit mode, Q0–Q17 are used and when in 9-bit mode, Q0–Q8 are
used, and the unused outputs, Q9-Q17 should not be connected. Outputs are not 5V tolerant regardless of the
stateof
OE.
REN
Read Enable
I
REN enables RCLK for reading data from the FIFO memory and offset registers.
RCLK/
Read Clock/
I
If Synchronous operation of the read port has been selected, when enabled by
REN, the rising edge of RCLK
RD
Read Strobe
reads data from the FIFO memory and offsets from the programmable registers. If
LD is LOW, the values loaded
into the offset registers is output on a rising edge of RCLK. If Asynchronous operation of the read port has been
selected, a rising edge on RD reads data from the FIFO in an Asynchronous manner.
REN should be tied LOW.
Asynchronous operation of the RCLK/RD input is only available in the BGA package.
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