- 您现在的位置：买卖IC网 > PDF目录9942 > IDT72V3676L10PF8 (IDT, Integrated Device Technology Inc)IC FIFO 16384X36 10NS 128QFP PDF资料下载
参数资料
| 型号： | IDT72V3676L10PF8 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 23/39页 |
| 文件大小： | 0K |
| 描述： | IC FIFO 16384X36 10NS 128QFP |
| 标准包装： | 1,000 |
| 系列： | 72V |
| 功能： | 异步 |
| 存储容量： | 576K（16K x 36） |
| 数据速率： | 100MHz |
| 访问时间： | 10ns |
| 电源电压： | 3.15 V ~ 3.45 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 128-LQFP |
| 供应商设备封装： | 128-TQFP（14x20） |
| 包装： | 带卷 (TR) |
| 其它名称： | 72V3676L10PF8 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页当前第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页
3
COMMERCIALTEMPERATURERANGE
IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFOTM
WITH BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
each port are independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide a simple
bidirectional interface between microprocessors and/or buses with synchro-
nous control.
CommunicationbetweeneachportmaybypasstheFIFOsviatwomailbox
registers. The mailbox registers' width matches the selected bus width of ports
B and C. Each mailbox register has a flag (
MBF1 and MBF2) to signal when
new mail has been stored.
TwokindsofresetareavailableontheseFIFOs:MasterResetandPartial
Reset. Master Reset initializes the read and write pointers to the first location
ofthememoryarrayandselectsserialflagprogramming,parallelflagprogram-
ming, or one of five possible default flag offset settings, 8, 16, 64, 256 or 1,024.
Each FIFO has its own, independent Master Reset pin,
MRS1 and MRS2.
PartialResetalsosetsthereadandwritepointerstothefirstlocationofthe
memory. Unlike Master Reset, any settings existing prior to Partial Reset (i.e.,
programmingmethodandpartialflagdefaultoffsets)areretained. PartialReset
is useful since it permits flushing of the FIFO memory without changing any
configuration settings. Each FIFO has its own, independent Partial Reset pin,
PRS1 and PRS2. Note that the Retransmit Mode, RTM pin must be LOW at
the point a partial reset is performed.
BothFIFO'shaveRetramsmitcapability,whenaRetransmitisperformed
on a respective FIFO only the read pointer is reset to the first memory location.
ARetransmitisperformedbyusingtheRetransmitMode,RTMpininconjunction
with the Retransmit pins
RT1 or RT2,for each respective FIFO. Note that the
two Retransmit pins
RT1 and RT2 are muxed with the Partial Reset pins.
These devices have two modes of operation: In the IDT Standard mode,
the first word written to an empty FIFO is deposited into the memory array. A
read operation is required to access that word (along with all other words
residing in memory). In the First Word Fall Through mode (FWFT), the first
word written to an empty FIFO appears automatically on the outputs, no read
operation required (Nevertheless, accessing subsequent words does neces-
sitate a formal read request). The state of the BE/
FWFT pin during Master
Reset determines the mode in use.
Each FIFO has a combined Empty/Output Ready Flag (
EFA/ORA and
EFB/ORB) and a combined Full/Input Ready Flag (FFA/IRA and FFC/
IRC). The
EF and FF functions are selected in the IDT Standard mode. EF
indicates whether or not the FIFO memory is empty.
FF shows whether the
memory is full or not. The IR and OR functions are selected in the First Word
FallThroughmode. IRindicateswhetherornottheFIFOhasavailablememory
locations. OR shows whether the FIFO has data available for reading or not.
It marks the presence of valid data on the outputs.
Each FIFO has a programmable Almost-Empty flag (
AEAandAEB)and
aprogrammableAlmost-Fullflag(
AFAandAFC). AEAandAEB indicatewhen
aselectednumberofwordsremainintheFIFOmemory.
AFAandAFCindicate
when the FIFO contains more than a selected number of words.
FFA/IRA, FFC/IRC, AFA and AFC are two-stage synchronized to the
Port Clock that writes data into its array.
EFA/ORA, EFB/ORB, AEA, and
AEBaretwo-stagesynchronizedtothePortClockthatreadsdatafromitsarray.
Programmable offsets for
AEA, AEB, AFA, AFC are loaded in parallel using
PortAorinserialviatheSDinput.Fivedefaultoffsetsettingsarealsoprovided.
The
AEA and AEB threshold can be set at 8, 16, 64, 256, and 1,024 locations
from the empty boundary and the
AFA and AFC threshold can be set at 8,
16,64,256or1,024locationsfromthefullboundary. Allthesechoicesaremade
using the FS0, FS1 and FS2 inputs during Master Reset.
Interspersed Parity can also be selected during a Master Reset of the
FIFO.IfInterspersedParityisselectedthenduringparallelprogrammingofthe
flag offset values, the device will ignore data line A8. If Non-Interspersed Parity
is selected then data line A8 will become a valid bit.
A Loopback function is provided on Port A. When the Loop feature is
selected via the
LOOP pin, the data output from FIFO2 will be directed to the
data input of FIFO1. If Loop is selected and Port A is set-up for write operation
via W/
RApin,thendataoutputfromFIFO2willbewrittentoFIFO1,butwillnot
be placed on the output Port A (A0-A35). If Port A is set-up for read operation
viaW/
RAthendataoutputfromFIFO2willbewrittenintoFIFO1andplacedonto
Port A (A0-A35). The Loop will continue to happen provided that FIFO1 is not
fullandFIFO2isnotempty.IfduringaLoopsequenceFIFO1becomesfullthen
any data that continues to be read out from FIFO2 will only be placed on the
PortA(A0-A35)lines,providedthatPortAisset-upforreadoperation.Ifduring
a Loop sequence the FIFO2 becomes empty, then the last word from FIFO2
willcontinuetobeclockedintoFIFO1untilFIFO1becomesfulloruntiltheLoop
function is stopped. The Loop feature can be useful when performing system
debugging and remote loopbacks.
Two or more FIFOs may be used in parallel to create wider data paths.
Suchawidthexpansionrequiresnoadditional,externalcomponents. Further-
more, two IDT72V3656/72V3666/72V3676 FIFOs can be combined with
unidirectional FIFOs capable of First Word Fall Through timing (i.e. the
SuperSync FIFO family) to form a depth expansion.
If, at any time, the FIFO is not actively performing a function, the chip will
automatically power down. During the power down state, supply current
consumption(ICC)isataminimum. Initiatinganyoperation(byactivatingcontrol
inputs) will immediately take the device out of the power down state.
The IDT72V3656/72V3666/72V3676 are characterized for operation from
0
°C to 70°C. Industrial temperature range (-40°C to +85°C) is available by
special order. They are fabricated using IDT’s high speed, submicron CMOS
technology.
相关PDF资料 |
PDF描述 |
|---|---|
| IDT72V3674L10PF8 | IC FIFO 16384X36 10NS 128QFP |
| VI-B5D-IV-F4 | CONVERTER MOD DC/DC 85V 150W |
| VI-B5D-IV-F2 | CONVERTER MOD DC/DC 85V 150W |
| VI-B5D-IV-F1 | CONVERTER MOD DC/DC 85V 150W |
| V150B48M250BF | CONVERTER MOD DC/DC 48V 250W |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT72V3676L15PF | 功能描述:IC FIFO 16384X36 15NS 128QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT72V3676L15PF8 | 功能描述:IC FIFO 16384X36 15NS 128QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT72V3680L10PF | 功能描述:IC FIFO SS 16384X36 10NS 128TQFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT72V3680L10PF8 | 功能描述:IC FIFO SS 16384X36 10NS 128TQFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT72V3680L10PFI | 制造商:Integrated Device Technology Inc 功能描述: |
发布紧急采购，3分钟左右您将得到回复。