参数资料
型号: IDT79RC32V334-133BB9
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 133 MHz, RISC MICROCONTROLLER, PBGA256
封装: PLASTIC, BGA-256
文件页数: 27/30页
文件大小: 652K
代理商: IDT79RC32V334-133BB9
6 of 30
November 1, 2001
79RC32334
mem_wait_n
Input
Memory Wait Negated Requires an external pullup.
SRAM/IOI/IOM modes: Allows external wait-states to be injected during last cycle before data is sampled.
DPM (dual-port) mode: Allows dual-port busy signal to restart memory transaction.
Alternate function: sdram_wait_n.
mem_245_oe_n
Output
Low
Memory FCT245 Output Enable Negated
Controls output enable to optional FCT245 transceiver bank by asserting during both reads and writes to a
memory or I/O bank.
mem_245_dt_r_n
Output
High
Memory FCT245 Direction Xmit/Rcv Negated Recommend an external pull-up.
Alternate function: cpu_dt_r_n. See CPU Core Specific Signals below.
output_clk
Output
High
Output Clock
Optional clock output.
PCI Interface
pci_ad[31:0]
I/O
PCI
PCI Multiplexed Address/Data Bus
Address driven by Bus Master during initial frame_n assertion, and then the Data is driven by the Bus Mas-
ter during writes; or the Data is driven by the Bus Slave during reads.
pci_cbe_n[3:0]
I/O
PCI
PCI Multiplexed Command/Byte Enable Bus
Command (not negated) Bus driven by the Bus Master during the initial frame_n assertion. Byte Enable
Negated Bus driven by the Bus Master during the data phase(s).
pci_par
I/O
PCI
PCI Parity
Even parity of the pci_ad[31:0] bus. Driven by Bus Master during Address and Write Data phases. Driven by
the Bus Slave during the Read Data phase.
pci_frame_n
I/O
PCI
PCI Frame Negated
Driven by the Bus Master. Assertion indicates the beginning of a bus transaction. De-assertion indicates the
last datum.
pci_trdy_n
I/O
PCI
PCI Target Ready Negated
Driven by the Bus Slave to indicate the current datum can complete.
pci_irdy_n
I/O
PCI
PCI Initiator Ready Negated
Driven by the Bus Master to indicate that the current datum can complete.
pci_stop_n
I/O
PCI
PCI Stop Negated
Driven by the Bus Slave to terminate the current bus transaction.
pci_idsel_n
Input
PCI Initialization Device Select
Uses pci_req_n[2] pin. See the PCI subsection.
pci_perr_n
I/O
PCI
PCI Parity Error Negated
Driven by the receiving Bus Agent 2 clocks after the data is received, if a parity error occurs.
pci_serr_n
I/O Open-
collector
PCI
System Error Requires an external pull-up.
Driven by any agent to indicate an address parity error, data parity during a Special Cycle command, or any
other system error.
pci_clk
Input
PCI Clock
Clock for PCI Bus transactions. Uses the rising edge for all timing references.
pci_rst_n
Input
PCI Reset Negated
Host mode: Resets all PCI related logic.
Satellite mode: with boot from PCI mode: Resets all PCI related logic and also warm resets the 32334.
pci_devsel_n
I/O
PCI
PCI Device Select Negated
Driven by the target to indicate that the target has decoded the present address as a target address.
Name
Type
Drive
Strength
Capability
Description
Table 1 Pin Descriptions (Part 2 of 7)
相关PDF资料
PDF描述
IDT79RC32V334-100BBI 32-BIT, 100 MHz, RISC MICROCONTROLLER, PBGA256
IDT79RC32V334-133BB8 32-BIT, 133 MHz, RISC MICROCONTROLLER, PBGA256
IDT79RC32V334-150BB9 32-BIT, 150 MHz, RISC MICROCONTROLLER, PBGA256
IDT79RC32V334-133BBI9 32-BIT, 133 MHz, RISC MICROCONTROLLER, PBGA256
IDT79RC32V364-100DAGI 32-BIT, 100 MHz, RISC PROCESSOR, PQFP144
相关代理商/技术参数
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