参数资料
型号: IDT82V2608BB
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 数字传输电路
英文描述: INVERSE MULTIPLEXING FOR ATM
中文描述: ATM/SONET/SDH SUPPORT CIRCUIT, PBGA208
封装: PLASTIC, BGA-208
文件页数: 25/98页
文件大小: 398K
代理商: IDT82V2608BB
INTERFACE
25
December 4, 2006
IDT82V2608
Inverse Multiplexing for ATM
3.3.5
REGISTER DESCRIPTION
Table-5 Input FIFO Data Length Register (INPUT_FIFO_LENGTH_REG)
(R/W, Address=00H)
Symbol
Position
Default
Description
-
7-5
0
Reserved.
Input_Message_Length[4:0]
4-0
0
These 5 bits contain the message length in the Input FIFO which should be written after the mes-
sage is sent to the Input FIFO. The valid length is from0 to 16 bytes.
Table-6 Output FIFO Data Length Register (OUTPUT_FIFO_LENGTH_REG)
(R, Address=01H)
Symbol
Position
Default
Description
-
7-5
0
Reserved.
Output_Message_Length[4:0]
4-0
0
These 5 bits contain the length of the message in the Output FIFO. Valid length is from0 to 16
bytes.
Table-7 Output FIFO Data Register (OUTPUT_FIFO_DATA_REG)
(R, Address=02H)
Symbol
Position
Default
Description
Output_Data[7:0]
7-0
0
These bits contain the data fromthe message Output FIFO. The complete message can be
retrieved by continuously reading this register.
Table-8 Input FIFO Data Register (INPUT_FIFO_DATA_REG)
(R/W, Address=03H)
Symbol
Position
Default
Description
Input_Data[7:0]
7-0
0
These bits contain data to be sent to the Input FIFO. By continuously writing to this register, a
complete message can be sent. Before the message is sent, the Input_FIFO_empty_state bit in
the EP_interrupt status register should be polled to see whether the Input FIFO is available for
writing. After the message is sent, the message length should be written to the EP_Tx_length reg-
ister.
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