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参数资料
| 型号： | IDT82V3255TF |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 通信及网络 |
| 英文描述： | WAN PLL |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP64 |
| 封装： | TQFP-64 |
| 文件页数： | 19/127页 |
| 文件大小： | 868K |
| 代理商： | IDT82V3255TF |
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IDT82V3255
WAN PLL
Functional Description
19
June 19, 2006
3.4
INPUT CLOCK PRE-DIVIDER
Each input clock is assigned an internal Pre-Divider. The Pre-Divider
is used to divide the clock frequency down to the DPLL required fre-
quency, which is no more than 38.88 MHz. For each input clock, the
DPLL required frequency is set by the corresponding IN_FREQ[3:0] bits.
If the input clock is of 2 kHz, 4 kHz or 8 kHz, the Pre-Divider is
bypassed automatically and the corresponding IN_FREQ[3:0] bits
should be set to match the input frequency; the input clock can be
inverted, as determined by the IN_2K_4K_8K_INV bit.
Each Pre-Divider consists of a HF (High Frequency) Divider (only
available for IN1_DIFF and IN2_DIFF), a DivN Divider and a Lock 8k
Divider, as shown in
Figure 3
.
The HF Divider, which is only available for IN1_DIFF and IN2_DIFF,
should be used when the input clock is higher than (
>
) 155.52 MHz. The
input clock can be divided by 4, 5 or can bypass the HF Divider, as
determined by the IN1_DIFF_DIV[1:0]/IN2_DIFF_DIV[1:0] bits corre-
spondingly.
Either the DivN Divider or the Lock 8k Divider can be used or both
can be bypassed, as determined by the DIRECT_DIV bit and the
LOCK_8K bit.
When the DivN Divider is used, the division factor setting should
observe the following order:
1. Select an input clock by the PRE_DIV_CH_VALUE[3:0] bits;
2. Write the lower eight bits of the division factor to the
PRE_DIVN_VALUE[7:0] bits;
3. Write the higher eight bits of the division factor to the
PRE_DIVN_VALUE[14:8] bits.
Once the division factor is set for the input clock selected by the
PRE_DIV_CH_VALUE[3:0] bits, it is valid until a different division factor
is set for the same input clock. The division factor is calculated as fol-
lows:
Division Factor = (the frequency of the clock input to the DivN
Divider ÷ the frequency of the DPLL required clock set by the
IN_FREQ[3:0] bits) - 1
The DivN Divider can only divide the input clock whose frequency is
lower than (
<
) 155.52 MHz.
When the Lock 8k Divider is used, the input clock is divided down to
8 kHz automatically.
The Pre-Divider configuration and the division factor setting depend
on the input clock on one of the clock input pin and the DPLL required
clock. Here is an example:
The input clock on the IN2_DIFF pin is 622.08 MHz; the DPLL
required clock is 6.48 MHz by programming the IN_FREQ[3:0] bits of
register IN2_DIFF to ‘0010’. Do the following step by step to divide the
input clock:
1. Use the HF Divider to divide the clock down to 155.52 MHz:
622.08 ÷ 155.52 = 4, so set the IN2_DIFF_DIV[1:0] bits to ‘01’;
2. Use the DivN Divider to divide the clock down to 6.48 MHz:
Set the PRE_DIV_CH_VALUE[3:0] bits to ‘0110’;
Set the DIRECT_DIV bit in Register IN2_DIFF_CNFG to ‘1’ and
the LOCK_8K bit in Register IN2_DIFF_CNFG to ‘0’;
155.52 ÷ 6.48 = 24; 24 - 1 = 23, so set the
PRE_DIVN_VALUE[14:0] bits to ‘10111’.
Figure 3. Pre-Divider for An Input Clock
Table 4: Related Bit / Register in Chapter 3.4
Bit
Register
Address (Hex)
IN1_DIFF_DIV[1:0]
IN2_DIFF_DIV[1:0]
IN_FREQ[3:0]
DIRECT_DIV
LOCK_8K
IN_2K_4K_8K_INV
PRE_DIV_CH_VALUE[3:0]
PRE_DIVN_VALUE[14:0]
IN1_DIFF_IN2_DIFF_HF_DIV_CNFG
18
IN1_CMOS_CNFG, IN2_CMOS_CNFG, IN1_DIFF_CNFG, IN2_DIFF_CNFG,
IN3_CNFG
16, 17, 19, 1A, 1D
FR_MFR_SYNC_CNFG
PRE_DIV_CH_CNFG
74
23
PRE_DIVN[14:8]_CNFG, PRE_DIVN[7:0]_CNFG
25, 24
input clock
DivN Divider
Lock 8k Divider
HF Divider
(for IN1_DIFF &
IN2_DIFF only)
Pre-Divider
IN1_DIFF_DIV[1:0] bits / IN2_DIFF_DIV[1:0] bits
DIRECT_DIV bit
LOCK_8K bit
DPLL required clock
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|---|---|
| IDT82V3255TFG | WAN PLL |
| IDT82V3280 | WAN PLL |
| IDT82V3280DQ | WAN PLL |
| IDT82V3280DQG | WAN PLL |
| IDT82V3280PF | WAN PLL |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT82V3255TFBLANK | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:WAN PLL |
| IDT82V3255TFG | 功能描述:IC PLL WAN SMC STRATUM 3 64-TQFP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1,500 系列:- 类型:时钟缓冲器/驱动器 PLL:是 主要目的:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 电源电压:3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:带卷 (TR) 其它名称:93786AFT |
| IDT82V3255TFG8 | 功能描述:IC PLL WAN SMC STRATUM 3 64-TQFP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1,500 系列:- 类型:时钟缓冲器/驱动器 PLL:是 主要目的:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 电源电压:3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:带卷 (TR) 其它名称:93786AFT |
| IDT82V3255TFGBLANK | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:WAN PLL |
| IDT82V3280 | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:WAN PLL |
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