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| 型号： | IDT82V3355TFG8 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 69/135页 |
| 文件大小： | 0K |
| 描述： | IC PLL WAN SYNC ETH 64-TQFP |
| 标准包装： | 1,250 |
| 类型： | 时钟/频率发生器，多路复用器 |
| PLL： | 是 |
| 主要目的： | 以太网，SONET/SDH，Stratum |
| 输入： | CMOS，LVDS，PECL |
| 输出： | CMOS，LVDS，PECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 3:2 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 622.08MHz |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-LQFP |
| 供应商设备封装： | 64-TQFP（10x10） |
| 包装： | 带卷 (TR) |
| 其它名称： | 82V3355TFG8 |
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IDT82V3355
SYNCHRONOUS ETHERNET WAN PLL
Functional Description
39
May 19, 2009
3.13.2
FRAME SYNC OUTPUT SIGNALS
An 8 kHz and a 2 kHz frame sync signals are output on the
FRSYNC_8K and MFRSYNC_2K pins if enabled by the 8K_EN and
2K_EN bits respectively. They are CMOS outputs.
The two frame sync signals are derived from the T0 APLL output and
are aligned with the output clock. They can be synchronized to one of
the three frame sync input signals.
One of the three frame sync input signals is selected, as determined
by the SYNC_BYPASS bit and the T0 selected input clock, as shown in
If the selected frame sync input signal with respect to the T0 selected
input clock is above a limit set by the SYNC_MON_LIMT[2:0] bits, an
external sync alarm will be raised and the selected frame sync input sig-
nal is disabled to synchronize the frame sync output signals. The exter-
nal sync alarm is cleared once the selected frame sync input signal with
respect to the T0 selected input clock is within the limit. If it is within the
limit, whether the selected frame sync input signal is enabled to synchro-
nize the frame sync output signal is determined by the SYNC_BYPASS
bit, the AUTO_EXT_SYNC_EN bit and the EXT_SYNC_EN bit. Refer to
Table 29 for details.
When the selected frame sync input signal is enabled to synchronize
the frame sync output signal, it should be adjusted to align itself with the
T0 selected input clock. Nominally, the falling edge of the selected frame
sync input signal is aligned with the rising edge of the T0 selected input
clock. The selected frame sync input signal may be 0.5 UI early/late or 1
UI late due to the circuit and board wiring delays. Setting the sampling of
the selected frame sync input signal by the SYNC_PHn[1:0] bits (n = 1,
2 or 3 corresponding to EX_SYNC1, EX_SYNC2 or EX_SYCN3 respec-
tively) will compensate this early/late. Refer to Figure 8 to Figure 11.
The EX_SYNC_ALARM_MON bit indicates whether the selected
frame sync input signal is in external sync alarm status. The external
sync alarm is indicated by the EX_SYNC_ALARM 1 bit. If the
EX_SYNC_ALARM 2 bit is ‘1’, the occurrence of the external sync alarm
will trigger an interrupt.
The 8 kHz and the 2 kHz frame sync output signals can be inverted
by setting the 8K_INV and 2K_INV bits respectively. The frame sync out-
puts can be 50:50 duty cycle or pulsed, as determined by the 8K_PUL
and 2K_PUL bits respectively. When they are pulsed, the pulse width is
defined by the period of OUT2; and they are pulsed on the position of
the falling or rising edge of the standard 50:50 duty cycle, as selected by
the 2K_8K_PUL_POSITION bit.
Figure 8. On Target Frame Sync Input Signal Timing
Figure 9. 0.5 UI Early Frame Sync Input Signal Timing
Table 28: Frame Sync Input Signal Selection
SYNC_BYPASS T0 Selected Input Clock
Selected Frame Sync Input
Signal
0
don’t-care
EX_SYNC1
1
IN1_CMOS or IN1_DIFF
EX_SYNC1
IN2_CMOS or IN2_DIFF
EX_SYNC2
IN3_CMOS
EX_SYNC3
none
Table 29: Synchronization Control
SYNC_BYPASS
AUTO_EXT_SYNC_EN
EXT_SYNC_EN
Synchronization
0
don’t-care
0
Disabled
01
Enabled
1
Disabled
1
don’t-care
Enabled
T0 selected
input clock
Output clocks
Selected frame
sync input signal
Frame sync
output signals
T0 selected
input clock
Output clocks
Selected frame
sync input signal
Frame sync
output signals
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT82V3355TFGBLANK | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:SYNCHRONOUS ETHERNET WAN PLL |
| IDT82V3358 | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:SYNCHRONOUS ETHERNET WAN PLL |
| IDT82V3358EDG | 功能描述:IC PLL WAN SYNC ETHERNET 64TQFP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1,500 系列:- 类型:时钟缓冲器/驱动器 PLL:是 主要目的:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 电源电压:3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:带卷 (TR) 其它名称:93786AFT |
| IDT82V3358EDG8 | 制造商:Integrated Device Technology Inc 功能描述:IC PLL WAN SYNC ETHERNET 64TQFP |
| IDT82V3380 | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:SYNCHRONOUS ETHERNET WAN PLL |
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