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参数资料
| 型号： | IP1206TRPBF |
| 厂商： | International Rectifier |
| 文件页数： | 23/30页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 30A/15A LGA |
| 产品变化通告： | (EP) Parts Discontinuation 25/May/2012 |
| 标准包装： | 750 |
| 系列： | iPOWIR™ |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 或 2 |
| 输出电压： | 0.8 V ~ 5.5 V |
| 输入电压： | 7.5 V ~ 14.5 V |
| PWM 型： | 电压模式 |
| 频率 - 开关： | 200kHz ~ 600kHz |
| 电流 - 输出： | 30A，15A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 36-BFLGA |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 36-LGA（9.25x15.5） |
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i P1206PbF
Compensation for Current Loop
(slave channel)
The slave error amplifier is differential
transconductance amplifier, in 2-phase
configuration the main goal for the slave channel
feedback loop is to control the inductor current to
Select a zero frequency for current loop (F o2 ) 1.5
times larger than zero cross frequency for
voltage loop (F o1 ).
F O 2 ? 1 . 5 % * F O 1
match the master channel inductor current as
well provides highest bandwidth and adequate
phase margin for overall stability. The following
H ( F O 2 ) = g m * R s 1 * R 2 *
V in
2 π * F O 2 * L 2 * V osc
= 1
- - - - ( 22 )
analysis is valid for both using external current
sense resistors and using DCR of inductor.
From (22), R2 can be expressed as:
G ( s ) = =
- - - - ( 20 )
The transfer function of power stage is
expressed by:
I L 2 ( s ) V in
V e sL 2 * V osc
R 2 =
V in =12V
1
g m * R s 1
*
2 π * F O 2 * L 2 * V osc
V in
- - - - ( 23 )
Where:
V in =Input voltage
L 2 =Output inductor
V osc =Oscillator Peak Voltage
As shown the G(s) is a function of inductor
current. The transfer function for compensation
network is given by equation (21), when using a
series RC circuit as shown in Fig 23.
I L2
V osc =1.25V
g m =2800umoh
L 2 =1uH
R s1 =DCR=2.4mOhm
F o2 =60kHz
This results to : R 2 =5.84K
The power stage of current loop has a dominant
pole (Fp) at frequency expressed by:
Fb2
L 2
F P =
R eq
2 π * L 2
R S2
Vp2
E/A2
Comp2
Ve
R eq = R ds ( on 1 ) * D + R ds ( on 2 ) * ( 1 ? D ) + R L
R S1
L 1
R 2
C 2
Where Rds(on1) is the on-resistance of control
FET, Rds(on2) is the on-resistance of
synchronous FET, RL is the DCR of output
I L1
Fig. 23: The Compensation network for current loop
inductance and D is the duty cycle
Req=9.48mOhm
R eq = R ds ( on ) + R L + R s
= ? ? g m * s 1 ? ? * ? ?
? ?
D ( s ) =
V e ( s ) ? R ? ? 1 + sC 2 R 2 ?
R s 2 ? R s 2 ? ? sC 2 ?
- - - - ( 21 )
Set the zero of compensator at 10 times the
dominant pole frequency FP, the compensator
? ? * ? ?
? ?
H ( s ) = R s 2 * ? ? g m * s 1 ? ? * ? ?
C 2 =
The loop gain function is:
H ( s ) = [ G ( s ) * D ( s ) * R s 2 ]
? R ? ? 1 + sR 2 C 2 ? ? V in ?
? R s 2 ? ? sC 2 ? ? sL 2 * V osc ?
capacitor, C2 can be expressed as:
F z = 10 * F P
1
2 π * R 2 * F z
C2=1nF
All designs should be tested for stability to verify
the calculated values.
www.irf.com
2/26/2008
23
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