参数资料
型号: IP1206TRPBF
厂商: International Rectifier
文件页数: 27/30页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 30A/15A LGA
产品变化通告: (EP) Parts Discontinuation 25/May/2012
标准包装: 750
系列: iPOWIR™
类型: 降压(降压)
输出类型: 可调式
输出数: 1 或 2
输出电压: 0.8 V ~ 5.5 V
输入电压: 7.5 V ~ 14.5 V
PWM 型: 电压模式
频率 - 开关: 200kHz ~ 600kHz
电流 - 输出: 30A,15A
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 36-BFLGA
包装: 带卷 (TR)
供应商设备封装: 36-LGA(9.25x15.5)

i P1206PbF
Fig. 27 Top component and via placement (Topside, transparent view down)
PCB Layout Guidelines
The following guidelines are recommended to reduce the parasitic values and optimize overall performance.
? All pads on the iP1206 footprint design need to be Solder-mask defined (see Figure 26). Also refer to
International Rectifier application notes AN1028 and AN1029 for further footprint design guidance.
? Place as many vias around the Power pads (VIN, VSW, and PGND) for both electrical and optimal thermal
performance.
? Vias in between the different power pads may overlap the pad opening and solder mask edge without the need
to plug the via hole. Vias with a 13mil drill hole and 25mil capture pad were used in this example.
? A minimum of six 10μF, X5R, 16V ceramic capacitors per iP1206 are recommended for the lowest loss due to
input capacitor ESR.
? Placement of the ceramic input capacitors is critical to optimize switching performance. In cases where there is
a space constraint on the top layer capacitors C3,C4, C7 and C8 can be placed on the bottom layer directly
below the footprints of C1, C2, C5 and C6.
? Dedicate at least two layers for PGND only.
? Duplicate the Power Nodes on multiple layers (refer to AN1029).
? Refer to AN-1030 for information on applying IPOWIR products in your thermal environment for Safe Operation.
www.irf.com
2/26/2008
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