参数资料
型号: IR22141SSPBF
厂商: International Rectifier
文件页数: 13/34页
文件大小: 0K
描述: IC DRIVER HALF BRIDGE SGL 24SSOP
标准包装: 55
配置: 半桥
输入类型: 非反相
延迟时间: 440ns
电流 - 峰: 2A
配置数: 1
输出数: 2
高端电压 - 最大(自引导启动): 1200V
电源电压: 11.5 V ~ 20 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 24-SSOP(0.209",5.30mm 宽)
供应商设备封装: 24-SSOP
包装: 管件
配用: IRMD2214SS-ND - KIT DESIGN EVAL BOARD IR2214SS
IRMD22141SS-ND - KIT DESIGN EVAL BOARD/IR22141SS
IR21141/IR22141SSPbF
Figure 13: High and Low Side Output Stage
SY_FLT
(external
hold)
FAULT/SD
(external hard
shutdown)
internal
HOLD
internal FAULT
(hard shutdown)
Q
Q
SET
CLR
S
R
DesatHS
DesatLS
UVCC
FLTCLR
Figure 14: Fault Management Diagram
The external sensing diode should have breakdown
voltage greater than 600 V (IR21141) or 1200 V
(IR22141), and low stray capacitance (in order to
minimize noise coupling and switching delays). The
diode is biased by an internal pull-up resistor R DSH/L
(equal to V CC /I DS- or V BS /I DS- ) or by a dedicated circuit
(see the active-bias section). To limit the current flowing
through DSH and DSL in case of desaturation an
external Schottky diode is required, as shown in Fig. 13.
When V CE increases, the voltage at the DSH or DSL pin
increases too. Being internally biased to the local supply,
the DSH/DSL voltage is automatically clamped. When
SY_FLT output pin (active low, see Fig. 14) reports the
gate driver status during the SSD sequence (t SS ). Once
the SSD has finished, SY_FLT releases, and the gate
driver generates a FAULT signal (see the FAULT/SD
section) by activating the FAULT/SD pin. This generates
a hard shutdown for both the high and low output stages
(HO=LO=low). Each driver is latched low until the fault is
cleared (see FLT_CLR).
Figure 14 shows the fault management circuit. In this
diagram DesatHS and DesatLS are two internal signals
that come from the output stages (see Fig. 13).
DSH/DSL exceeds the V DESAT+
threshold, the
comparator triggers (see Fig. 13). The comparator’s
output is filtered in order to avoid false desaturation
detection by externally induced noise; pulses shorter
than t DS are filtered out. To avoid detecting a false
desaturation event during IGBT turn on, the desaturation
circuit is disabled by a blanking signal (T BL , see blanking
block in Fig. 13). This time is the estimated maximum
IGBT turn on time and must be not exceeded by proper
gate resistance sizing. When the IGBT is not completely
saturated after T BL , desaturation is detected and the
driver will turn off.
Eligible desaturation signals initiate the SSD sequence.
While in SSD, the driver’s output goes to a high
impedance state and the SSD pull-down is activated to
turn off the IGBT through the SSDH/SSDL pin. The
www.irf.com
13
It must be noted that while in SSD, both the
undervoltage fault and external SD are masked until the
end of SSD. Desaturation protection is working
independently by the other control pin and it is disabled
only when the output status is off.
1.4.4 Fault Management in Multi-Phase Systems
In a system with two or more gate drivers the
IR21141/IR22141 devices must be connected as shown
in Fig. 15.
? 2009 International Rectifier
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