参数资料
型号: IR22141SSPBF
厂商: International Rectifier
文件页数: 15/34页
文件大小: 0K
描述: IC DRIVER HALF BRIDGE SGL 24SSOP
标准包装: 55
配置: 半桥
输入类型: 非反相
延迟时间: 440ns
电流 - 峰: 2A
配置数: 1
输出数: 2
高端电压 - 最大(自引导启动): 1200V
电源电压: 11.5 V ~ 20 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 24-SSOP(0.209",5.30mm 宽)
供应商设备封装: 24-SSOP
包装: 管件
配用: IRMD2214SS-ND - KIT DESIGN EVAL BOARD IR2214SS
IRMD22141SS-ND - KIT DESIGN EVAL BOARD/IR22141SS
IR21141/IR22141SSPbF
diode is required between DSH and VB and between
DSL and Vcc, as shown in Fig 13. A diode similar to the
1N5818 is good enough to protect DSH and DSL.
R DSH/L
while an additional stage is maintained in the active state
for a limited time (t on1 ). This feature boosts the total
driving capability in order to accommodate both a fast
gate charge to the plateau voltage and dV/dt control in
switching.
100K ohm
At turn off, a single n-channel sinks up to 3 A (I O- ) and
offers a low impedance path to prevent the self-turn on
due to the parasitic Miller capacitance in the power
switch.
100 ohm
V DSH/L
Figure 16: R DSH/L Active Biasing
1.6 Output Stage
The structure is shown in Fig. 13 and consists of two
turn on stages and one turn off stage. When the driver
turns on the IGBT (see Fig. 8), a first stage is activated
1.7 Timing and Logic State Diagrams Description
The following figures show the input/output logic
diagram. Figure 17 shows the SY_FLT and FAULT/SD
signals as outputs, whereas Fig. 18 shows them as
inputs.
A
B
C
D
E
F
G
HIN
LIN
DSH
DSL
SY_FLT
FAULT/SD
FLT_CLR
HO(HOP/HON)
LO(LOP/LON)
Figure 17: I/O Timing Diagram with SY_FLT and FAULT/SD as Output
A B
C
D
E
F
HIN
LIN
SY_FLT
FAULT/SD
FLT_CLR
HO (HOP/HON)
LO (LOP/LON)
Figure 18: I/O Logic Diagram with SY_FLT and FAULT/SD as Input
www.irf.com
15
? 2009 International Rectifier
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