参数资料
型号: IR3503MTRPBF
厂商: International Rectifier
文件页数: 20/39页
文件大小: 0K
描述: IC CTRL XPHASE VR11.0/1 32-MLPQ
标准包装: 1
系列: XPhase3™
应用: 处理器
电流 - 电源: 8mA
电源电压: 4.75 V ~ 7.5 V
工作温度: 0°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 32-VFQFN 裸露焊盘
供应商设备封装: 32-MLPQ(5x5)
包装: 标准包装
其它名称: IR3503MTRPBFDKR
IR3503
Start-up Sequence
The IR3503 has a programmable soft-start function to limit the surge current during the converter start-up. A
capacitor connected between the SS/DEL and LGND pins controls soft start timing, over-current protection delay
and hiccup mode timing. A charge current of 52.5 μ A and discharge current of 4 μ A control the up slope and down
slope of the voltage at the SS/DEL pin respectively. Figure 11 depicts start-up sequence of converter with VR 11.1
VID. If there is no fault, as the ENABLE is asserted, the SS/DEL pin will start charging. The error amplifier output
EAOUT is clamped low until SS/DEL reaches 1.4 V. The error amplifier will then regulate the converter’s output
voltage to match the SS/DEL voltage less the 1.4 V offset until the converter output reaches the 1.1 V boot voltage.
The SS/DEL voltage continues to increase until it rises above the 3.0 V threshold of VID delay comparator. The VID
set inputs are then activated and VDAC pin transitions to the level determined by the VID inputs. The SS/DEL
voltage continues to increase until it rises above 3.92 V and allows the VRRDY signal to be asserted. SS/DEL finally
settles at 4.0 V, indicating the end of the soft start. The remote sense amplifier has a very low operating range of 50
mV in order to achieve a smooth soft start of output voltage without bump. The rise time of the VCCL applied to the
system should be at least greater than 25 μ s.
The VCCL under voltage lock-out, VID fault modes, over current, as well as a low signal on the ENABLE input
immediately sets the fault latch, which causes the EAOUT pin to drive low turning off the phase IC drivers. The
VRRDY pin also drives low and SS/DEL begin to discharge until the voltage reaches 0.2 V. If the fault has cleared
the fault latch will be reset by the discharge comparator allowing a normal soft start to occur.
Other fault conditions, such as over voltage, open sense lines, open loop monitor, and open daisy chain, set
different fault latches, which start discharging SS/DEL, pull down EAOUT voltage and drive VRRDY low. However,
the latches can only be reset by cycling VCCL power.
VCC
(12V)
ENABLE
VID
1.1V
VDAC
4.0V
3.92V
3V
1.4V
SS/DEL
EAOUT
VOUT
VRRDY
START DELAY (TD1)
SOFT START
TIME (TD2)
VID SAMPLE
TIME (TD3)
VRRDY DELAY
TIME (TD4+TD5)
NORMAL OPERATION
TD4
TD5
Figure 11: Start-up Sequence of the Converter with Boot Voltage
Current Monitor (IMON)
The control IC generates a current monitor signal IMON using the VDRP voltage and the VDAC reference, as
shown in Figure 12. This voltage is thermally compensated for the inductor DCR variation. The voltage at this pin
reports the average load current information without being referenced to VDAC. The slope of the IMON signal with
Page 20 of 39
February 12, 2010
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