参数资料
型号: IR3522MTRPBF
厂商: International Rectifier
文件页数: 9/32页
文件大小: 0K
描述: IC CTRL XPHASE3 DDR/VVT 32-MLPQ
标准包装: 3,000
系列: XPhase3™
应用: 处理器
电流 - 电源: 7mA
电源电压: 4.75 V ~ 7.5 V
工作温度: 0°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 32-VFQFN 裸露焊盘
供应商设备封装: 32-MLPQ(5x5)
包装: 带卷 (TR)
IR3522
SYSTEM THEORY OF OPERATION
PWM Control Method
The PWM block diagram of the xPHASE3 TM architecture is shown in Figure 3. Feed-forward voltage mode control
with trailing edge modulation is used to provide system control. A voltage type error amplifier with high-gain and
wide-bandwidth, located in the Control IC, is used for the voltage control loop. The feed-forward control is
performed by the phase ICs as a result of sensing the Input voltage (FET’s drain voltage). The PWM ramp slope
will change with the input voltage and automatically compensate for changes in the input voltage. The input voltage
can change due to variations in the silver box output voltage or due to the wire and PCB-trace voltage drop related
to changes in load current.
.
IR3522 CONTROL IC
GATE DRIVE
VOLTAGE
PHSOUT
IR3506 PHASE IC
VIN
CLOCK GENERATOR
CLKOUT
CLKIN
C LK Q
D
PWM
VCCH
PHSOUT
PHSIN
PHSIN
PWM
COMPARATOR
LATCH
S
RESET
DOMINANT
GATEH
SW
C BST
VOSNS1+
VOUT1
EAIN
VC CL
-
+
R
VCCL
COUT
GND
REMOTE SENSE
ENABLE
GATEL
AMPLIFIER
VOUT1
VID6
RAMP
DISCHARGE
PGND
VOSNS1-
CLAMP
VREF1
ERROR
LGND
SHARE ADJUST
ERROR AMPLIFIER
AMPLIFIER
VREF1_FAST
EAOUT1
R CP1
IOUT
3K
-
VID6
VID6
+
CURRENT
SENSE
AMPLIFIER
CSIN+
CC P12
R FB12
RF B11
VID6
VID6 +
C CS
R CS
C CP11
+
CSIN-
FB1
C FB1
DACIN
PHSOUT
CLKIN
C LK Q
D
IR3506 PHASE IC
PWM
VCCH
PHSIN
PWM
COMPARATOR
LATCH
S
RESET
DOMINANT
GATEH
SW
C BST
EAIN
VC CL
-
+
R
VCCL
ENABLE
VID6
RAMP
DISCHARGE
CLAMP
SHARE ADJUST
ERROR AMPLIFIER
CURRENT
GATEL
PGND
IOUT
3K
-
VID6
VID6
+
SENSE
AMPLIFIER
CSIN+
VID6
VID6 +
+
CSIN-
C CS
R CS
DACIN
Figure 3 - PWM Block Diagram
Frequency and Phase Timing Control
The system oscillator is located in the Control IC and is programmable from 250 kHz to 9 MHZ by an external
resistor. The control IC clock signal (CLKOUT) is connected to CLKIN of all the phase ICs. The phase timing of the
phase ICs is controlled by a daisy chain loop. The control IC phase clock output (PHSOUT) is connected to the
phase clock input (PHSIN) of the first phase IC, and PHSOUT of the first phase IC is connected to PHSIN of the
second phase IC, etc. The last phase IC (PHSOUT) is connected back to PHSIN of the control IC to complete the
loop. During power up, the control IC sends out clock signals from both CLKOUT and PHSOUT pins and detects
the feedback at PHSIN pin to determine the phase number and monitor any fault in the daisy chain loop. Figure 4
shows the phase timing for a four phase converter.
Page 9
V3.01
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