参数资料
型号: IRS2330JTRPBF
厂商: International Rectifier
文件页数: 4/39页
文件大小: 0K
描述: IC BRIDGE DVR 3PH 600V 44-PLCC
标准包装: 1
配置: 3 相桥
输入类型: 反相
延迟时间: 500ns
电流 - 峰: 250mA
配置数: 1
输出数: 3
高端电压 - 最大(自引导启动): 600V
电源电压: 10 V ~ 20 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 44-PLCC(32 引线)
供应商设备封装: 44-PLCC,32 引线
包装: 标准包装
产品目录页面: 1382 (CN2011-ZH PDF)
其它名称: IRS2330JTRPBFDKR
IRS233(0,2)(D)(S&J)PbF
Recommended Operating Conditions
The Input/Output logic timing diagram is shown in figure 1. For proper operation the device should be used within the
recommended conditions. All voltage parameters are absolute voltage referenced to V SO. The V S offset rating is
tested wit h all supplies biased at 15 V differential.
Symbol
V B1,2,3
V S1,2,3
V St1,2,3
V HO1,2,3
V CC
V SS
V LO1,2,3
V IN
V FLT
V CAO
V CA-
T A
Definition
High-side floating supply voltage
Static high-side floating offset voltage
Transient high-side floating offset voltage
High-side floating output voltage
Low-side and Logic fixed supply voltage
Logic ground
Low-side output voltage
Logic input voltage (HIN1,2,3, LIN1,2,3 & ITRIP)
FAULT output voltage
Operational amplifier output voltage
Operational amplifier inverting input voltage
Ambient temperature
Min.
V S1,2,3 +10
V SO -8 (Note1)
-50 (Note2)
V S1,2,3
10
-5
0
V SS
V SS
V SS
V SS
-40
Max.
V S1,2,3 +20
600
600
V B1,2,3
20
5
V CC
V SS + 5
V CC
V SS + 5
V SS + 5
125
Units
V
°C
Note 1: Logic operational for V S of (V SO -8 V) to (V SO +600 V). Logic state held for V S of (V SO -8 V) to (V SO – V BS ) .
Note 2: Operational for transient negative VS of VSS - 50 V with a 50 ns pulse width. Guaranteed by design. Refer to
the Application Information section of this datasheet for more details.
Note 3: CAO input pin is internally clamped with a 5.2 V zener diode.
Dynamic Electrical Characteristics
V BIAS (V CC , V BS1,2,3 ) = 15 V, V SO1,2,3 = V SS , C L = 1000 pF, T A = 25 ° C unless otherwise specified.
Symbol
Definition
Min Typ Max Units Test Conditions
t on
t off
t r
t f
t itrip
t bl
t flt
t flt, in
Turn-on propagation delay
Turn-off propagation delay
Turn-on rise time
Turn-off fall time
ITRIP to output shutdown propagation delay
ITRIP blanking time
ITRIP to FAULT indication delay
Input filter time (all six inputs)
400
400
400
350
500
500
80
35
660
400
550
325
700
700
125
55
920
870
V S1,2,3 = 0 V to 600 V
V S1,2,3 = 0 V
t fltclr
LIN1,2,3 to FAULT clear time (2330/2)
5300 8500 13700
ns
DT
MDT
Deadtime:
Deadtime matching: :
(IRS2330(D))
(IRS2332(D))
(IRS2330(D))
(IRS2332(D))
1300 2000 3100
500 700 1100
— — 400
— — 140
V IN = 0 V & 5 V
without
external deadtime
V IN = 0 V & 5 V
MT
Delay matching time (t ON , t OFF )
50
without
external deadtime
larger than DT
PM
Pulse width distortion
75
PM input 10 s
NOTE: For high side PWM, HIN pulse width must be > 1.5 usec
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