![](http://datasheet.mmic.net.cn/170000/IS61VPS51218A-200TQI_datasheet_8913140/IS61VPS51218A-200TQI_22.png)
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Integrated Silicon Solution, Inc.
Rev. I
01/13/09
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
TEST DATA OUT (TDO)
TheTDOoutputpinisusedtoseriallyclockdata-outfrom
theregisters.Theoutputisactivedependingonthecurrent
state of the TAP state machine (see TAP Controller State
Diagram).TheoutputchangesonthefallingedgeofTCK
andTDOisconnectedtotheLeastSignificantBit(LSB)
of any register.
PERFORMINg A TAP RESET
AResetisperformedbyforcingTMSHIGH(Vdd) for five
risingedgesofTCK.RESETmaybeperformedwhilethe
SRAMisoperatinganddoesnotaffectitsoperation.At
power-up,theTAPisinternallyresettoensurethatTDO
comesupinahigh-Zstate.
TAP REgISTERS
RegistersareconnectedbetweentheTDIandTDOpins
andallowdatatobescannedintoandoutoftheSRAM
test circuitry
. Onlyoneregistercanbeselectedatatime
throughtheinstructionregisters.Dataisseriallyloaded
intotheTDIpinontherisingedgeofTCKandoutputon
theTDOpinonthefallingedgeofTCK.
Instruction Register
Three-bitinstructionscanbeseriallyloadedintothein-
structionregister.Thisregisterisloadedwhenitisplaced
between the TDI and TDO pins. (See TAPControllerBlock
Diagram) Atpower-up,theinstructionregisterisloaded
with the IDCODE instruction. It is also loaded with the
IDCODEinstructionifthecontrollerisplacedinareset
state as previously described.
WhentheTAPcontrollerisintheCaptureIRstate,thetwo
leastsignificantbitsareloadedwithabinary“01”patternto
allow for fault isolation of the board level serial test path.
Bypass Register
Tosavetimewhenseriallyshiftingdatathroughregisters,
itissometimesadvantageoustoskipcertainstates.The
bypassregisterisasingle-bitregisterthatcanbeplaced
betweenTDIandTDOpins.Thisallowsdatatobeshifted
through the SRAM with minimal delay.The bypass reg-
isterissetLOW(Vss)whentheBYPASSinstructionis
executed.
Boundary Scan Register
Theboundaryscanregisterisconnectedtoallinputand
output pins on the SRAM. Several no connect (NC) pins are
also included in the scan register to reserve pins for higher
densitydevices.Thex36configurationhasa75-bit-long
registerandthex18configurationalsohasa75-bit-long
register.The boundary scan register is loaded with the
contentsoftheRAMInputandOutputringwhentheTAP
controllerisintheCapture-DRstateandthenplacedbe-
tween the TDI and TDO pins when the controller is moved
to the Shift-DRstate.TheEXTEST,SAMPLE/PRELOAD
andSAMPLE-Zinstructionscanbeusedtocapturethe
contentsoftheInputandOutputring.
TheBoundaryScanOrdertablesshowtheorderinwhich
thebitsareconnected.Eachbitcorrespondstooneofthe
bumpsontheSRAMpackage.TheMSBoftheregisteris
connectedtoTDI,andtheLSBisconnectedtoTDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit
codeduringtheCapture-DRstatewhentheIDCODEcom-
mandisloadedtotheinstructionregister.TheIDCODE
ishardwiredintotheSRAMandcanbeshiftedoutwhen
theTAPcontrollerisintheShift-DRstate.TheIDregister
has vendor code and other information described in the
IdentificationRegisterDefinitionstable.
Scan Register Sizes
Register
Bit Size
Name
(x18)
(x36)
Instruction
3
Bypass
1
ID
32
BoundaryScan
75
IDENTIFICATION REgISTER DEFINITIONS
Instruction Field
Description
256K x 36
512K x 18
RevisionNumber (31:28)
Reservedforversionnumber.
xxxx
DeviceDepth (27:23)
DefinesdepthofSRAM.256Kor512K
00111
01000
DeviceWidth (22:18)
DefineswidthoftheSRAM.x36orx18
00100
00011
ISSIDeviceID (17:12)
Reservedforfutureuse.
xxxxx
ISSIJEDECID (11:1)
AllowsuniqueidentificationofSRAMvendor.
00011010101
00011010101
IDRegisterPresence (0)
IndicatethepresenceofanIDregister.
1