参数资料
型号: IS62UP25616LL-55BI
厂商: INTEGRATED SILICON SOLUTION INC
元件分类: SRAM
英文描述: 256K X 16 STANDARD SRAM, 55 ns, PBGA48
封装: MINI, BGA-48
文件页数: 12/13页
文件大小: 83K
代理商: IS62UP25616LL-55BI
IS62Ux25616 SERIES
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
TARGET SPECIFICATION SR070-0T
05/01/99
ISSI
TARGET SPECIFICATION
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
-55
-70
-100
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
tWC
Write Cycle Time
55
70
100
ns
tSCE
CE to Write End
45
60
80
ns
tAW
Address Setup Time to Write End
45
60
80
ns
tHA
Address Hold from Write End
0
0
0
ns
tSA
Address Setup Time
0
0
0
ns
tPWB
LB, UB Valid to End of Write
45
60
80
ns
tPWE1
WE Pulse Width
45
60
80
ns
tPWE2
WE Pulse Width
45
60
80
ns
tSD
Data Setup to Write End
25
30
40
ns
tHD
Data Hold from Write End
0
0
0
ns
tHZWE(3)
WE LOW to High-Z Output
30
30
40
ns
tLZWE(3)
WE HIGH to Low-Z Output
5
5
5
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0.4V to
2.2V and output loading specified in Figure 1.
2. The internal write time is defined by the overlap of
CE LOW and UB or LB, and WE LOW. All signals must be in valid states
to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to
the rising or falling edge of the signal that terminates the write.
3. Tested with the load in Figure 1. Transition is measured
±200 mV from steady-state voltage. Not 100% tested.
t RC
t OHA
t AA
t DOE
t LZOE
t ACE
t LZCE
t HZOE
HIGH-Z
DATA VALID
t HZB
ADDRESS
OE
CE
LB, UB
DOUT
t HZCE
t BA
t LZB
AC WAVEFORMS
READ CYCLE NO. 2(1,3)
Notes:
1.
WE is HIGH for a Read Cycle.
2. The device is continuously selected.
OE, CE, UB, or LB = VIL.
3. Address is valid prior to or coincident with
CE LOW transition.
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