参数资料
型号: IS63LV1024L-8TI
元件分类: SRAM
英文描述: 128K X 8 STANDARD SRAM, 8 ns, PDSO32
封装: 0.400 INCH, TSOP2-32
文件页数: 15/16页
文件大小: 260K
代理商: IS63LV1024L-8TI
8
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. M
01/29/2010
IS63LV1024
IS63LV1024L
AC WAVEFORMS
WRITE CYCLE NO. 2(1) (WE Controlled, OE = HIGH during Write Cycle)
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)
Notes:
1. The internal write time is defined by the overlap of
CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if
OE > VIH.
DATA UNDEFINED
LOW
t WC
VALID ADDRESS
t PWE1
t AW
t HA
HIGH-Z
t HD
t SA
t HZWE
ADDRESS
CE
WE
DOUT
DIN
OE
DATAIN VALID
t LZWE
t SD
CE_WR2.eps
DATA UNDEFINED
t WC
VALID ADDRESS
LOW
t PWE2
t AW
t HA
HIGH-Z
t HD
tSA
t HZWE
ADDRESS
CE
WE
DOUT
DIN
OE
DATAIN VALID
t LZWE
t SD
CE_WR3.eps
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