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参数资料
| 型号： | ISD4003-08MSI |
| 厂商： | WINBOND ELECTRONICS CORP |
| 元件分类： | 音频合成 |
| 英文描述： | 480 SEC, SPEECH SYNTHESIZER WITH RCDG, PDSO28 |
| 封装： | 0.1200 INCH, PLASTIC, SOIC-28 |
| 文件页数： | 13/37页 |
| 文件大小： | 392K |
| 代理商： | ISD4003-08MSI |
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20
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]
8285E–AVR–02/2013
Figure 8-3.
On-chip data SRAM access cycles.
8.3
EEPROM data memory
The Atmel ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P contains 512 bytes of
data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written.
The EEPROM has an endurance of at least 100,000 write/erase cycles. This section describes the access
between the EEPROM and the CPU, specifying the EEPROM Address Registers, the EEPROM Data Register,
and the EEPROM Control Register.
For a detailed description of SPI, JTAG and Parallel data downloading to the EEPROM, see ”Serial Downloading”
on page 271, ”Programming via the JTAG Interface” on page 275, and ”Parallel Programming Parameters, Pin
Mapping, and Commands” on page 260 respectively.
8.3.1
EEPROM Read/Write access
The EEPROM Access Registers are accessible in the I/O space.
The write access time for the EEPROM is given in Table 8-1 on page 21. A self-timing function, however, lets the
user software detect when the next byte can be written. If the user code contains instructions that write the
EEPROM, some precautions must be taken. In heavily filtered power supplies, V
CC is likely to rise or fall slowly on
power-up/down. This causes the device for some period of time to run at a voltage lower than specified as mini-
mum for the clock frequency used. See ”Preventing EEPROM corruption” on page 23 for details on how to avoid
problems in these situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When
the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed.
The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential).
See ”Register description” on page 24 for supplementary description for each register bit:
1.
Wait until EEWE becomes zero.
2.
Wait until SPMEN in SPMCSR becomes zero.
3.
Write new EEPROM address to EEAR (optional).
4.
Write new EEPROM data to EEDR (optional).
5.
Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR.
6.
Within four clock cycles after setting EEMWE, write a logical one to EEWE.
clk
WR
RD
Data
Address
Address valid
T1
T2
T3
Compute Address
Read
Wr
ite
CPU
Memory Access Instruction
Next Instruction
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