参数资料
型号: ISD4003-08MSI
厂商: WINBOND ELECTRONICS CORP
元件分类: 音频合成
英文描述: 480 SEC, SPEECH SYNTHESIZER WITH RCDG, PDSO28
封装: 0.1200 INCH, PLASTIC, SOIC-28
文件页数: 8/37页
文件大小: 392K
代理商: ISD4003-08MSI
16
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]
8285E–AVR–02/2013
is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable bit is
set, and will then be executed by order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not nec-
essarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will
not be triggered.
When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction
before any pending interrupt is served.
Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when
returning from an interrupt routine. This must be handled by software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be
executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example
shows how this can be used to avoid interrupts during the timed EEPROM write sequence.
When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pend-
ing interrupts, as shown in this example.
7.8.1
Interrupt response time
The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. After four clock
cycles the program vector address for the actual interrupt handling routine is executed. During this four clock cycle
period, the Program Counter is pushed onto the Stack. The vector is normally a jump to the interrupt routine, and
this jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction
is completed before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt exe-
Assembly code example
in
r16, SREG
; store SREG value
cli
; disable interrupts during timed sequence
sbi
EECR, EEMWE
; start EEPROM write
sbi
EECR, EEWE
out
SREG, r16
; restore SREG value (I-bit)
C code example
char
cSREG;
cSREG = SREG; /* store SREG value */
/* disable interrupts during timed sequence */
__disable_interrupt();
EECR |= (1<<EEMWE); /* start EEPROM write */
EECR |= (1<<EEWE);
SREG = cSREG; /* restore SREG value (I-bit) */
Assembly code example
sei
; set Global Interrupt Enable
sleep
; enter sleep, waiting for interrupt
; note: will enter sleep before any pending
; interrupt(s)
C code example
__enable_interrupt(); /* set Global Interrupt Enable */
__sleep(); /* enter sleep, waiting for interrupt */
/* note: will enter sleep before any pending interrupt(s) */
相关PDF资料
PDF描述
ISD4003-04MZD 240 SEC, SPEECH SYNTHESIZER WITH RCDG, PBGA19
ISD4003-04MZI 240 SEC, SPEECH SYNTHESIZER WITH RCDG, PBGA19
ISD4003-05MZD 300 SEC, SPEECH SYNTHESIZER WITH RCDG, PBGA19
ISD4003-05MZI 300 SEC, SPEECH SYNTHESIZER WITH RCDG, PBGA19
ISD4003-06MZD 360 SEC, SPEECH SYNTHESIZER WITH RCDG, PBGA19
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