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参数资料
| 型号： | ISL12029 |
| 厂商： | Intersil Corporation |
| 英文描述： | Real Time Clock/Calendar with EEPROM(带EEPROM实时时钟/日历) |
| 中文描述： | 实时时钟/日历带有EEPROM（带EEPROM的实时时钟/日历） |
| 文件页数： | 14/28页 |
| 文件大小： | 426K |
| 代理商： | ISL12029 |
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14
FN6206.6
October 18, 2006
The effective series load capacitance is the combination of
C
X1
and C
X2
:
For example, C
LOAD
(ATR = 00000) = 12.5pF,
C
LOAD
(ATR = 100000) = 4.5pF, and C
LOAD
(ATR = 011111)
= 20.25pF. The entire range for the series combination of
load capacitance goes from 4.5pF to 20.25pF in 0.25pF
steps. Note that these are typical values.
DTR Register - DTR2, DTR1, DTR0: Digital
Trimming Register
The digital trimming Bits DTR2, DTR1 and DTR0 adjust the
number of counts per second and average the ppm error to
achieve better accuracy.
DTR2 is a sign bit. DTR2 = 0 means frequency
compensation is > 0. DTR2 = 1 means frequency
compensation is < 0.
DTR1 and DTR0 are scale bits. DTR1 gives 10ppm
adjustment and DTR0 gives 20ppm adjustment.
A range from -30ppm to +30ppm can be represented by
using three bits above.
PWR Register: SBIB, BSW, VTS2, VTS1, VTS0
SBIB: - Serial Bus Interface (Enable)
The serial bus can be disabled in battery backup mode by
setting this bit to “1”. This will minimize power drain on the
battery. The Serial Interface can be enabled in battery
backup mode by setting this bit to “0”. (default is “0”). See
Reset and Power Control section.
BSW: Power Control Bit
The Power Control bit, BSW, determines the conditions for
switching between V
DD
and Back Up Battery. There are two
options.
Option 1. Standard: Set “BSW = 0”
Option 2. Legacy/Default Mode: Set “BSW = 1”
See Power Control Operation later in this document for more
details. Also see “I
2
C Communications During Battery
backup and LVR Operation” in the Applications section for
important details.
VTS2, VTS1, VTS0: V
RESET
Select Bits
The ISL12029 is shipped with a default V
DD
threshold
(V
RESET
) per the ordering information table. This register is
a nonvolatile with no protection, therefore any writes to this
location can change the default value from that marked on
the package. If not changed with a nonvolatile write, this
value will not change over normal operating and storage
conditions. However, ISL12029 has four (4) additional
selectable levels to fit the customers application. Levels are:
4.64V(default), 4.38V, 3.09V, 2.92V and 2.63V. The V
RESET
selection is via 3 bits (VTS2, VTS1 and VTS0). See Table 6.
Care should be taken when changing the V
RESET
select bits.
If the V
RESET
voltage selected is higher than V
DD
, then the
device will go into RESET and unless V
DD
is increased, the
device will no longer be able to communicate using the I
2
C
bus.
Device Operation
Writing to the Clock/Control Registers
Changing any of the bits of the clock/control registers
requires the following steps:
1. Write a 02h to the Status Register to set the Write Enable
Latch (WEL). This is a volatile operation, so there is no
delay after the write. (Operation preceded by a start and
ended with a stop).
2. Write a 06h to the Status Register to set both the Register
Write Enable Latch (RWEL) and the WEL bit. This is also
a volatile cycle. The zeros in the data byte are required.
(Operation proceeded by a start and ended with a stop).
Write all eight bytes to the RTC registers, or one byte to the
SR, or one to five bytes to the control registers. This
sequence starts with a start bit, requires a slave byte of
“11011110” and an address within the CCR and is terminated
by a stop bit. A write to the EEPROM registers in the CCR
will initiate a nonvolatile write cycle and will take up to 20ms
to complete. A write to the RTC registers (SRAM) will require
much shorter cycle time (t = t
BUF
). Writes to undefined areas
TABLE 5. DIGITAL TRIMMING REGISTERS
DTR REGISTER
ESTIMATED FREQUENCY
PPM
DTR2
DTR1
DTR0
0
0
0
0
0
1
0
+10
0
0
1
+20
0
1
1
+30
1
0
0
0
1
1
0
-10
1
0
1
-20
1
1
1
-30
CLOAD
X1
----------
X2
----------
+
----------------------------------
=
CLOAD
-----------------------------------------------------------------------------------------------------------------------------
9
+
pF
=
TABLE 6.
VTS2
VTS1
VTS0
V
RESET
0
0
0
4.64V
0
0
1
4.38V
0
1
0
3.09V
0
1
1
2.92V
1
0
0
2.63V
ISL12029
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL12029_10 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Real Time Clock/Calendar with I2C Busa?￠ and EEPROM |
| ISL12029_1012 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Real Time Clock/Calendar with I2C Bus? and EEPROM |
| ISL12029A | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Real Time Clock/Calendar with I2C Bus? and EEPROM |
| ISL12029AIB27Z | 功能描述:实时时钟 REAL TIME CLKRTC W/ EPROM 2 63VSET 14 RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 总线接口:I2C 日期格式:DW:DM:M:Y 时间格式:HH:MM:SS RTC 存储容量:64 B 电源电压-最大:5.5 V 电源电压-最小:1.8 V 最大工作温度:+ 85 C 最小工作温度: 安装风格:Through Hole 封装 / 箱体:PDIP-8 封装:Tube |
| ISL12029AIB27Z-T | 功能描述:实时时钟 REAL TIME CLKRTC W/ EPROM 2 63VSET 14 RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 总线接口:I2C 日期格式:DW:DM:M:Y 时间格式:HH:MM:SS RTC 存储容量:64 B 电源电压-最大:5.5 V 电源电压-最小:1.8 V 最大工作温度:+ 85 C 最小工作温度: 安装风格:Through Hole 封装 / 箱体:PDIP-8 封装:Tube |
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