参数资料
型号: ISL12029
厂商: Intersil Corporation
英文描述: Real Time Clock/Calendar with EEPROM(带EEPROM实时时钟/日历)
中文描述: 实时时钟/日历带有EEPROM(带EEPROM的实时时钟/日历)
文件页数: 20/28页
文件大小: 426K
代理商: ISL12029
20
FN6206.6
October 18, 2006
.
ACKNOWLEDGE POLLING
Disabling of the inputs during nonvolatile write cycles can be
used to take advantage of the typical 5ms write cycle time.
Once the stop condition is issued to indicate the end of the
master’s byte load operation, the ISL12029 initiates the
internal nonvolatile write cycle. Acknowledge polling can
begin immediately. To do this, the master issues a start
condition followed by the Memory Array Slave Address Byte
for a write or read operation (AEh or AFh). If the ISL12029 is
still busy with the nonvolatile write cycle then no ACK will be
returned. When the ISL12029 has completed the write
operation, an ACK is returned and the host can proceed with
the read or write operation. Refer to the flow chart in
Figure 24. Note: Do not use the CCR Slave byte (DEh or
DFh) for Acknowledge Polling.
Read Operations
There are three basic read operations: Current Address
Read, Random Read, and Sequential Read.
Current Address Read
Internally the ISL12029 contains an address counter that
maintains the address of the last word read incremented by
one. Therefore, if the last read was to address n, the next
read operation would access data from address n+1. On
power up, the sixteen bit address is initialized to 0h. In this
way, a current address read immediately after the power-on
reset can download the entire contents of memory starting at
the first location.Upon receipt of the Slave Address Byte with
the R/W bit set to one, the ISL12029 issues an
acknowledge, then transmits eight data bits. The master
terminates the read operation by not responding with an
acknowledge during the ninth clock and issuing a stop
condition. Refer to Figure 23 for the address, acknowledge,
and data transfer sequence.
S
T
A
R
T
S
T
O
P
SLAVE
ADDRESS
WORD
ADDRESS 1
DATA
A
C
K
A
C
K
A
C
K
SDA BUS
SIGNALS FROM
THE SLAVE
SIGNALS FROM
THE MASTER
0
A
C
K
WORD
ADDRESS 0
1
1
1
1
0 0 0 0 0 0 0
FIGURE 20. BYTE WRITE SEQUENCE
ADDRESS
15
ADDRESS
10
6 BYTES
6 BYTES
ADDRESS=5
ADDRESS POINTER ENDS
AT ADDR= 5
FIGURE 21. WRITING
12
BYTES TO A
16
-BYTE MEMORY PAGE STARTING AT ADDRESS
10
WORD
ADDRESS 0
S
T
A
R
T
S
T
O
P
SLAVE
ADDRESS
WORD
ADDRESS 1
DATA
(n)
A
C
K
A
C
K
A
C
K
SDA BUS
SIGNALS FROM
THE SLAVE
SIGNALS FROM
THE MASTER
0
DATA
(1)
A
C
K
1
n
16 for EEPROM array
1
n
8 for CCR
1
1
1
1
0 0 0 0 0 0 0
FIGURE 22. PAGE WRITE SEQUENCE
ISL12029
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