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参数资料
| 型号： | ISL6244HRZ-T |
| 厂商： | Intersil |
| 文件页数： | 15/25页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM 32-QFN |
| 标准包装： | 6,000 |
| PWM 型： | 电流/电压模式 |
| 输出数： | 4 |
| 频率 - 最大： | 4MHz |
| 占空比： | 75% |
| 电源电压： | 4.75 V ~ 5.25 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -10°C ~ 100°C |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
ISL6244
ISL6244 INTERNAL CIRCUIT
EXTERNAL CIRCUIT
EXTERNAL CIRCUIT
ISL6244 INTERNAL CIRCUIT
+ 5V
R C
C C
COMP
+5V
VCC
ERROR AMPLIFIER
ENABLE
3.64k ?
FB
-
COMPARATOR
EN
R FB
IOUT
+
V COMP
POR
+
REFERENCE
CIRCUIT
-
1.40k ?
VDIFF
I RAMP
VOLTAGE
OV LATCH
SIGNAL
1.23V (±2%)
I AVG
V RAMP
IDEAL DIODES
FIGURE 20. POWER SEQUENCING USING THRESHOLD-
SENSITIVE ENABLE (EN) FUNCTION
FIGURE 21. RAMP CURRENT AND VOLTAGE FOR
REGULATING SOFT-START SLOPE
AND DURATION
Second, the ISL6244 features an enable input (EN) for
power sequencing between the controller bias voltage and
another voltage rail. The enable comparator holds the
ISL6244 in shutdown until the voltage at EN rises above
1.23V. The enable comparator has about 90mV of hysteresis
to prevent bounce. It is important that the driver ICs reach
their POR level before the ISL6244 becomes enabled. The
schematic in Figure 20 demonstrates sequencing the
ISL6244 with the ISL620X family of Intersil MOSFET drivers
which require 5V bias.
The ideal diodes in Figure 21 assure that the controller tries
to regulate its output to the lower of either the reference
voltage or V RAMP . Since I RAMP creates an initial offset
across R FB of (R FB x 160 μ A), the first PWM pulse will not be
seen until V RAMP is greater than the R FB I RAMP offset. This
produces a delay after the ISL6244 enables before the
output voltage starts moving. For example, if VID = 1.5V,
R FB = 1k ? and T SS = 8.3ms, the delay time can be
expressed using Equation 11.
t DELAY = --------------------------------------------------- = 560 μ s
1.4 ( VID )
R FB 160 × 10 – 6
The 11111 VID code is reserved as a signal to the controller
that no load is present. The controller will enter shutdown
mode after receiving this code and will start up upon
receiving any other code. This code is not intended as a
T SS
1 + -----------------------------------------
(EQ. 11)
means of enabling the controller when a load is present.
To enable the controller, VCC must be greater than the POR
threshold; the voltage on EN must be greater than 1.23V;
Following the delay, the soft start ramps linearly until V RAMP
reaches VID. For the system described above, this first
linear ramp will continue for approximately
t RAMP1 = ----------- – t DELAY
and VID cannot be equal to 11111. Once these conditions
are true, the controller immediately initiates a soft-start
T SS
1.4
(EQ. 12)
sequence.
Soft-Start
The soft-start time, t SS , is determined by an 11-bit counter
that increments with every pulse of the phase clock. For
example, a converter switching at 250kHz per phase has a
soft-start time of
= 5.27ms
The final portion of the soft-start sequence is the time
remaining after V RAMP reaches VID and before I RAMP gets to
zero. This is also characterized by a slight change in the slope
of the output voltage ramp which, for the current example,
exists for a time of
T SS = ------------- = 8.3ms
2048
f SW
(EQ. 10)
t RAMP2 = T SS – t RAMP1 – t DELAY
(EQ. 13)
During the soft-start interval, the soft-start voltage, V RAMP ,
increases linearly from zero to 140% of the programmed
DAC voltage. At the same time a current source, I RAMP , is
decreasing from 160 μ A down to zero. These signals are
connected as shown in Figure 21 (I OUT may or may not be
connected to FB depending on the particular application).
15
= 2.34ms
This behavior is seen in the example in Figure 22 of a
converter switching at 500kHz. For this converter, R FB is
set to 2.67k ? leading to T SS = 4.0ms, t DELAY = 700ns,
t RAMP1 = 2.23ms, and t RAMP2 = 1.17ms.
FN9106.3
December 28, 2004
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