参数资料
型号: ISL6244HRZ-T
厂商: Intersil
文件页数: 22/25页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM 32-QFN
标准包装: 6,000
PWM 型: 电流/电压模式
输出数: 4
频率 - 最大: 4MHz
占空比: 75%
电源电压: 4.75 V ~ 5.25 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -10°C ~ 100°C
封装/外壳: 32-VFQFN 裸露焊盘
包装: 带卷 (TR)
ISL6244
Figures 29 and 30 provide the same input RMS current
information for three and four phase designs respectively.
Use the same approach to selecting the bulk capacitor type
and number as described above.
0.6
0.3
I C,PP = 0
I C,PP = 0.5 I O
0.4
0.2
I C,PP = 0.25 I O
I C,PP = 0.75 I O
0.2
I C,PP = 0
I C,PP = 0.5 I O
I C,PP = 0.75 I O
0.1
0
0
0.2
0.4
0.6
0.8
1.0
DUTY CYCLE (V IN/ V O )
FIGURE 31. NORMALIZED INPUT-CAPACITOR RMS
CURRENT vs DUTY CYCLE FOR SINGLE-PHASE
0
0 0.2 0.4 0.6 0.8 1.0
DUTY CYCLE (V IN/ V O )
FIGURE 29. NORMALIZED INPUT-CAPACITOR RMS
CURRENT vs DUTY CYCLE FOR 3-PHASE
CONVERTER
Low capacitance, high-frequency ceramic capacitors are
needed in addition to the bulk capacitors to suppress leading
and falling edge voltage spikes. The result from the high
current slew rates produced by the upper MOSFETs turn on
and off. Select low ESL ceramic capacitors and place one as
close as possible to each upper MOSFET drain to minimize
board parasitics and maximize suppression.
CONVERTER
For example, compare the input rms current requirements of
a two-phase converter versus that of a single phase.
Assume both converters have a duty cycle of 0.25,
maximum sustained output current of 40A, and a ratio of
I C,PP to I O of 0.5. The single phase converter would require
17.3 Arms current capacity while the two-phase converter
would only require 10.9 Arms. The advantages become
even more pronounced when output current is increased
and additional phases are added to keep the component
cost down relative to the single phase approach.
Layout Considerations
0.3
I C,PP = 0
I C,PP = 0.25 I O
I C,PP = 0.5 I O
I C,PP = 0.75 I O
Printed circuit board (PCB) layout is very important in high
frequency switching converter design. With components
switching at greater than 200kHz, the resulting current
transitions from one device to another cause voltage spikes
across the interconnecting impedances and parasitic circuit
0.2
0.1
elements. These voltage spikes can degrade efficiency, lead
to device over-voltage stress, radiate noise into sensitive
nodes, and increase thermal stress on critical components.
Careful component placement and PCB layout minimizes
the voltage spikes in the converter.
The following multi-layer printed circuit board layout
strategies minimize the impact of board parasitics on
converter performance and optimize the heat-dissipating
0
0
0.2
0.4
0.6
0.8
1.0
capabilities of the printed-circuit board. This section
highlights some important practices which should not be
DUTY CYCLE (V IN/ V O )
FIGURE 30. NORMALIZED INPUT-CAPACITOR RMS
CURRENT vs DUTY CYCLE FOR 4-PHASE
CONVERTER
MULTIPHASE RMS IMPROVEMENT
Figure 31 is provided as a reference to demonstrate the
dramatic reductions in input-capacitor RMS current upon the
implementation of the multiphase topology.
22
overlooked during the layout process.
Component Placement
Determine the total implementation area and orient the
critical switching components first. Symmetry is very
important in multiphase converter placement and the
switching components dictate how the available space is
filled. The switching components carry large amounts of
energy and tend to generate high levels of noise. A tight
layout of the output inductors and MOSFETs with short, wide
FN9106.3
December 28, 2004
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