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| 型号： | ISL6244HRZ-T |
| 厂商： | Intersil |
| 文件页数： | 18/25页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM 32-QFN |
| 标准包装： | 6,000 |
| PWM 型： | 电流/电压模式 |
| 输出数： | 4 |
| 频率 - 最大： | 4MHz |
| 占空比： | 75% |
| 电源电压： | 4.75 V ~ 5.25 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -10°C ~ 100°C |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
ISL6244
UPPER MOSFET POWER CALCULATION
In addition to r DS(ON) losses, a large portion of the upper-
MOSFET losses are due to currents conducted across the
input voltage (V IN ) during switching. Since a substantially
higher portion of the upper-MOSFET losses are dependent
on switching frequency, the power calculation is more
complex. Upper MOSFET losses can be divided into
separate components involving the upper-MOSFET
switching times; the lower-MOSFET body-diode reverse-
Current Sensing
The ISEN pins are denoted ISEN1, ISEN2, ISEN3 and
ISEN4. The resistors connected between these pins and
their respective phase nodes determine the gains in the
load-line regulation loop and the channel-current balance
loop. Select the values for these resistors based on the room
temperature r DS(ON) of the lower MOSFETs; the full-load
operating current, I FL ; and the number of phases, N
according to Equation 20 (see also Figure 15).
R ISEN = ----------------------- )
I FL
recovery charge, Q rr ; and the upper MOSFET r DS(ON)
conduction loss.
r DS ( ON
50 × 10 – 6
--------
N
(EQ. 20)
When the upper MOSFET turns off, the lower MOSFET does
not conduct any portion of the inductor current until the
voltage at the phase node falls below ground. Once the
lower MOSFET begins conducting, the current in the upper
MOSFET falls to zero as the current in the lower MOSFET
ramps up to assume the full inductor current. In Equation 16,
the required time for this commutation is t 1 and the
approximated associated power loss is P UP,1 .
In certain circumstances, it may be necessary to adjust the
value of one or more of the ISEN resistors. This can arise
when the components of one or more channels are inhibited
from dissipating their heat so that the affected channels run
hotter than desired (see the section entitled Channel-Current
Balance ). In these cases, chose new, smaller values of R ISEN
for the affected phases. Choose R ISEN,2 in proportion to the
desired decrease in temperature rise in order to cause
I PP ? ?
I M
P UP , 1 ≈ V IN ? ------ + --------- ? ? ---- 1 ? f S
(EQ. 16)
R ISEN , 2 = R ISEN ---------- 2
t
? N 2 ? ? 2 ?
The upper MOSFET begins to conduct and this transition
proportionally less current to flow in the hotter phase.
? T
? T 1
(EQ. 21)
P UP , 2 ≈ V IN ? ------ – --------- ? ? ---- 2 ? f S
P UP , 3 = V IN Q rr f S
occurs over a time t 2 . In Equation 17, the approximate power
loss is P UP,2 .
? I M I PP ? ? t ? (EQ. 17)
? N 2 ? ? 2 ?
A third component involves the lower MOSFET’s reverse-
recovery charge, Q rr . Since the inductor current has fully
commutated to the upper MOSFET before the lower-
MOSFET’s body diode can draw all of Q rr , it is conducted
through the upper MOSFET across VIN. The power
dissipated as a result is P UP,3 and is approximately
(EQ. 18)
In Equation 21, make sure that ? T 2 is the desired temperature
rise above the ambient temperature, and ? T 1 is the measured
temperature rise above the ambient temperature. While a
single adjustment according to Equation 21 is usually
sufficient, it may occasionally be necessary to adjust R ISEN
two or more times to achieve perfect thermal balance
between all channels.
Load-Line Regulation Resistor
The load-line regulation resistor is labeled R FB in Figure
17. Its value depends on the desired full-load droop voltage
(V DROOP in Figure 17). If Equation 20 is used to select
each ISEN resistor, the load-line regulation resistor is as
shown in Equation 22.
Finally, the resistive part of the upper MOSFET’s is given in
Equation 19 as P UP,4 .
– 6
V DROOP
R FB = -------------------------
50 × 10
(EQ. 22)
I PP2
? I M ?
P UP , 4 ≈ r DS ( ON ) ? ------ ? d + ----------
? N ? 12
2
(EQ. 19)
If one or more of the ISEN resistors was adjusted for thermal
balance, as in Equation 21, the load-line regulation resistor
In this case, of course, r DS(ON) is the on resistance of the
upper MOSFET.
should be selected according to Equation 23. Where I FL is
the full-load operating current and R ISEN(n) is the ISEN
resistor connected to the n th ISEN pin.
I FL r DS ( ON )
The total power dissipated by the upper MOSFET at full load
can now be approximated as the summation of the results
from Equations 16, 17, 18 and 19. Since the power
V DROOP
R FB = --------------------------------
∑ R ISEN ( n )
n
(EQ. 23)
equations depend on MOSFET parameters, choosing the
correct MOSFETs can be an iterative process that involves
repetitively solving the loss equations for different MOSFETs
and different switching frequencies until converging upon the
best solution.
18
Compensation
The two opposing goals of compensating the voltage
regulator are stability and speed. Depending on whether the
regulator employs the optional load-line regulation as
described in Load-Line Regulation, there are two distinct
methods for achieving these goals.
FN9106.3
December 28, 2004
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| ISL6247CR-T | 功能描述:IC REG CTRLR PWM 40-QFN RoHS:否 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:4,000 系列:- PWM 型:电压模式 输出数:1 频率 - 最大:1.5MHz 占空比:66.7% 电源电压:4.75 V ~ 5.25 V 降压:是 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 85°C 封装/外壳:40-VFQFN 裸露焊盘 包装:带卷 (TR) |
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