参数资料
| 型号： | ISL6263CRZ |
| 厂商： | Intersil |
| 文件页数： | 10/19页 |
| 文件大小： | 0K |
| 描述： | IC VREG CORE 5BIT 1PHASE 32-QFN |
| 标准包装： | 60 |
| 应用： | 转换器，Intel IMVP-6 |
| 输入电压： | 5 V ~ 25 V |
| 输出数： | 1 |
| 输出电压： | 0.41 V ~ 1.29 V |
| 工作温度： | -10°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 供应商设备封装： | 32-QFN（5x5） |
| 包装： | 管件 |
ISL6263
TABLE 2. VID TABLE FOR INTEL IMVP-6+ V CCGFX
CORE (Continued)
Power-On Reset
The ISL6263 is disabled until the voltage at the VDD pin has
VID4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VID3
0
0
0
0
0
0
1
1
1
1
1
1
1
1
VID2
0
0
1
1
1
1
0
0
0
0
1
1
1
1
VID1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
VID0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
V CCGFX
(V)
0.82400V
0.79825V
0.77250V
0.74675V
0.72100V
0.69525V
0.66950V
0.64375V
0.61800V
0.59225V
0.56650V
0.54075V
0.51500V
0.41200V
increased above the rising VDD power-on reset (POR)
V DD_THR threshold voltage. The controller will become
disabled when the voltage at the VDD pin decreases below
the falling POR V DD_THF threshold voltage.
Start-Up Timing
Figure 4 shows the ISL6263 start-up timing. Once VDD has
ramped above V DD_THR , the controller can be enabled by
pulling the VR_ON pin voltage above the input-high
threshold V VR_ONH . Approximately 100μs later, the soft-start
capacitor C SOFT begins slewing to the designated VID
set-point as it is charged by the soft-start current source I SS .
The V CCGFX output voltage of the converter follows the
V SOFT voltage ramp to within 10% of the VID set-point then
counts 6 switching cycles, then changes the open-drain
output of the PGOOD pin to high impedance. During
soft-start, the regulator always operates in continuous
conduction mode (CCM).
VR_ON
Theory of Operation
The R 3 Modulator
The heart of the ISL6263 is Intersil’s Robust-Ripple-
Regulator (R 3 ) Technology?. The R 3 modulator is a hybrid
of fixed frequency PWM control, and variable frequency
hysteretic control that will simultaneously affect the PWM
switching frequency and PWM duty cycle in response to
input voltage and output load transients.
The term “Ripple” in the name “Robust-Ripple-Regulator”
refers to the synthesized voltage-ripple signal V R that
appears across the internal ripple-capacitor C R. The V R
signal is a representation of the output inductor ripple
current. Transconductance amplifiers measuring the input
voltage of the converter and the output set-point voltage
V SOFT , together produce the voltage-ripple signal V R .
A voltage window signal V W is created across the VW and
COMP pins by sourcing a current proportional to g m V soft
through a parallel network consisting of resistor R FSET and
capacitor C FSET. The synthesized voltage-ripple signal V R
along with similar companion signals are converted into
PWM pulses.
The PWM frequency is proportional to the difference in
amplitude between V W and V COMP . Operating on these
large-amplitude, low noise synthesized signals allows the
ISL6263 to achieve lower output ripple and lower phase jitter
than either conventional hysteretic or fixed frequency PWM
controllers. Unlike conventional hysteretic converters, the
ISL6263 has an error amplifier that allows the controller to
maintain tight voltage regulation accuracy throughout the
VID range from 0.41200V to 1.28750V.
10
90%
~100μs
V SOFT /V CCGFX
PGOOD
6 SWITCHING CYCLES
FIGURE 4. ISL6263 START-UP TIMING
Static Regulation
The V CCGFX output voltage will be regulated to the value set
by the VID inputs per Table 2. A true differential amplifier
connected to the VSEN and RTN pins implements processor
socket Kelvin sensing for precise core voltage regulation at
the GPU voltage sense points.
As the load current increases from zero, the V CCGFX output
voltage will droop from the VID set-point by an amount
proportional to the IMVP-6+ load line. The ISL6263 can
accommodate DCR current sensing or discrete resistor
current sensing. The DCR current sensing uses the intrinsic
series resistance of the output inductor as shown in the
application circuit of Figure 2. The discrete resistor current
sensing uses a shunt connected in series with the output
inductor as shown in the application circuit of Figure 3. In
both cases the signal is fed to the non-inverting input of the
DROOP amplifier at the VSUM pin, where it is measured
differentially with respect to the output voltage of the
converter at the VO pin and amplified. The voltage at the
FN9213.2
June 10, 2010
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| ISL6263CRZ-T | 功能描述:直流/直流开关调节器 1 PHS INT DC/DC BUCK CNTRLR FOR INTEL RoHS:否 制造商:International Rectifier 最大输入电压:21 V 开关频率:1.5 MHz 输出电压:0.5 V to 0.86 V 输出电流:4 A 输出端数量: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:PQFN 4 x 5 |
| ISL6263DEVAL1Z | 功能描述:EVAL BAORD 1 FOR ISL6263D RoHS:是 类别:编程器，开发系统 >> 评估板 - DC/DC 与 AC/DC（离线）SMPS 系列:* 产品培训模块:Obsolescence Mitigation Program 标准包装:1 系列:True Shutdown™ 主要目的:DC/DC，步升 输出及类型:1，非隔离 功率 - 输出:- 输出电压:- 电流 - 输出:1A 输入电压:2.5 V ~ 5.5 V 稳压器拓扑结构:升压 频率 - 开关:3MHz 板类型:完全填充 已供物品:板 已用 IC / 零件:MAX8969 |
| ISL6263DHRZ | 功能描述:IC VREG 3BIT 1PHASE 32-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,000 系列:- 应用:电源，ICERA E400，E450 输入电压:4.1 V ~ 5.5 V 输出数:10 输出电压:可编程 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:42-WFBGA，WLCSP 供应商设备封装:42-WLP 包装:带卷 (TR) |
| ISL6263DHRZ-T | 功能描述:IC VREG 3BIT 1PHASE 32-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6263EVAL1 | 制造商:Intersil Corporation 功能描述:ISL6263 EVALUATION BOARD 1 - IMVP LICENSE REQUIRED - Bulk |
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